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6b49b34cc5
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rename to TRVE
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2025-11-18 20:58:49 +01:00 |
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9c4e2d17a2
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Add support for addiw and lui
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2025-10-21 14:46:02 +02:00 |
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19568f855e
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Add a todo
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2025-10-14 18:22:09 +02:00 |
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7a519924cb
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Move funct3 values to rvi.rs instead of being in opcodes.rs
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2025-10-14 18:21:28 +02:00 |
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6bd31e73fb
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some debugging stuff and SECOND OPCODE!
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2025-10-10 19:01:04 +02:00 |
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bf5562df54
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Make fields of DeviceEntry public
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2025-10-09 20:27:20 +02:00 |
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5274828b81
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Make some constants and type aliases public
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2025-10-09 20:26:09 +02:00 |
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ee5f5a2ec4
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FIRST INSTRUCTION WORKING
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2025-10-07 20:23:59 +02:00 |
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361b36fbd1
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Make sure unsupported/illegal instructions are caught
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2025-10-07 20:16:27 +02:00 |
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dbd022f9c9
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Make fields and register access functions of Core accessible to the rest of the emulator
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2025-10-07 20:12:09 +02:00 |
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908be749ac
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Make fields of MemConfig public to allow creating one
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2025-10-07 17:04:20 +02:00 |
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52952840aa
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I guess its a working execution loop?
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2025-10-04 14:07:42 +02:00 |
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bb0007707c
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Swap out execution status for instructions returning an InstructionResult
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2025-10-03 13:28:02 +02:00 |
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4632fe29ce
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Initial instruction execution code i guess
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2025-09-30 18:39:14 +02:00 |
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f5ac1a132f
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Allow identification of the type of memory (ram or mmio) backing a specific page
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2025-09-28 21:13:29 +02:00 |
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3163b43fa4
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base core state & instruction decoder
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2025-09-27 21:43:10 +02:00 |
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5919041f07
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actually no NOW the memory interface is "done"
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2025-09-27 17:48:56 +02:00 |
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4a2272ae49
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Initial stuff and memory implementation
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2025-09-27 16:38:06 +02:00 |
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282740cb59
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Initial Readme
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2025-09-27 16:37:41 +02:00 |
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8de29e77b5
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Initial commit
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2025-09-06 12:38:12 +02:00 |
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