taitep/trve
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Commit Graph

  • 6b6b778ab0 some cleanup main taitep 2026-01-29 21:26:44 +01:00
  • bbfa20befe Replace custom UART with a sifive uart subset taitep 2026-01-29 19:07:43 +01:00
  • 36e6ec1006 Implement Zalrsc taitep 2026-01-13 16:46:53 +01:00
  • d3e8af85a6 Add the files and decode logic for RVA taitep 2026-01-12 17:25:02 +01:00
  • 3451a8227c Remove RamVersionClaim::reset as ive figured out it wont be needed taitep 2026-01-09 20:23:11 +01:00
  • d1b4cc7b56 Add some documentation in the cli help output taitep 2026-01-06 23:14:37 +01:00
  • 9861187fa6 Implement the memory version system that will be necessary for LR/SC taitep 2026-01-06 21:50:47 +01:00
  • 07e755340e remove get_atomic_(d)word because its not used yet and the idea for how atomics will be done will have to be reworked taitep 2026-01-02 16:21:20 +01:00
  • ceb7f2f172 Apply some clippy-suggested fixes taitep 2026-01-02 12:55:42 +01:00
  • 21fb6cbc8b Switch from std::mpsc channels to crossbeam taitep 2026-01-02 12:44:50 +01:00
  • bbc9e0b9ff 2026! Updating LICENSE file now and individual file comments when those files are updated taitep 2026-01-01 09:15:25 +01:00
  • 7fcfc031ef Stop rust-analyzer from complaining about the big endian host error taitep 2025-12-31 13:19:04 +01:00
  • 21a8479ce9 Make MMIO devices not have control of the address of exceptions taitep 2025-12-31 13:16:32 +01:00
  • 09fe12f516 Change some ordering in core.rs and deduplicate core command handling taitep 2025-12-31 09:33:14 +01:00
  • 0f0e844223 Finish RV64M taitep 2025-12-30 20:53:57 +01:00
  • 5a383956c9 Improve exception dumps and general debug info, make the emulator capable of running the riscv ISA tests, and perform some general fixes i found while making it pass the tests for RV64I taitep 2025-12-30 20:18:23 +01:00
  • 6a0e5e63c1 Implement DIV taitep 2025-12-30 17:27:42 +01:00
  • e5c5312566 Implement MUL taitep 2025-12-30 16:56:09 +01:00
  • 9a9bef7dd7 Remove consts.rs and just use plain types taitep 2025-12-28 12:01:39 +01:00
  • 8024af6b13 Implement ECALL and EBREAK, the final RV64I instructions! taitep 2025-12-27 21:47:22 +01:00
  • 5c008bfc04 Add exception values (what will go in mtval/stval) taitep 2025-12-27 21:33:39 +01:00
  • b5d36b7969 Initial FENCE implementation taitep 2025-12-27 21:03:24 +01:00
  • 970c1adcb0 Add checks to make sure that ram has a size that is a multiple of 8 taitep 2025-12-27 20:52:32 +01:00
  • 6a3920895b Relicense to BSD 2-Clause to align better with the RISC-V community taitep 2025-12-27 12:44:55 +01:00
  • 67406a9c48 Fix some warnings taitep 2025-12-27 11:55:19 +01:00
  • 9f8e9ec380 Implement a GDB stub and fix another huge issue in S-type immediate decoding taitep 2025-12-27 11:48:36 +01:00
  • a64fcaa3b5 Make execload respect the static ram start taitep 2025-12-26 19:32:55 +01:00
  • 34034dd5db Make macros for R/I-type operations and use them to implement basically every single one i think taitep 2025-12-26 18:14:32 +01:00
  • 75e843f5f9 Make branches macros and implement all of them taitep 2025-12-26 16:06:30 +01:00
  • 528b519ce9 (BIG CHANGE) memory handling has changed, MMIO is now a 2 level page table, misaligned access supported, addresses not internally split to page and offset immediately, all load/store instructions implemented. Might still have bugs taitep 2025-12-26 14:20:27 +01:00
  • 6d9efb7eb8 Small refactor in exception handling in core.rs taitep 2025-12-24 16:14:54 +01:00
  • 44394b3d19 Update README to mention ELF support taitep 2025-12-24 14:11:29 +01:00
  • 66c63ab63c Add a default implementation for the memory device interface that just returns access faults taitep 2025-12-24 14:06:16 +01:00
  • 09d9064372 EXCEPTION SYSTEM (initial version - may change later) taitep 2025-12-24 13:56:41 +01:00
  • 3f789442c0 some linker script updates to work even more properly for newlib i think taitep 2025-12-24 11:42:55 +01:00
  • 96c2cbf7ae remove unused imports in main.rs taitep 2025-12-23 20:04:14 +01:00
  • 8ed4845d58 ADD ELF SUPPORT taitep 2025-12-23 19:56:42 +01:00
  • 36faa1e39c Add license headers to files missing them taitep 2025-12-23 19:22:11 +01:00
  • 43bae12ea0 Comment out the unused 'Pause' instruction result taitep 2025-12-23 18:46:38 +01:00
  • 0c6a540a85 Implement SRLI taitep 2025-12-23 18:42:50 +01:00
  • 23392a55df Implement SH taitep 2025-12-23 18:31:04 +01:00
  • f38114dbd7 Remove some debug messages i forgot taitep 2025-12-23 11:01:28 +01:00
  • c6da147d50 Implement BLT taitep 2025-12-23 09:51:53 +01:00
  • 643a39c24a Fix s-type immediate decoding taitep 2025-12-23 09:51:32 +01:00
  • 1b409cd14e Improve error messaging taitep 2025-12-23 09:51:09 +01:00
  • 976bd688b0 Remove an unused import in main.rs taitep 2025-12-23 08:57:43 +01:00
  • 0ac363e203 Implement LW taitep 2025-12-22 22:48:57 +01:00
  • 7a22570a0f Improve the debug messages when invalid instructions are found (again) taitep 2025-12-22 22:46:45 +01:00
  • 2b5eb96187 Implement BLTU taitep 2025-12-22 21:17:38 +01:00
  • be1b1b9fe6 Implement LH taitep 2025-12-22 21:15:24 +01:00
  • 5cbaf2dc66 Implement BGEU taitep 2025-12-22 20:08:16 +01:00
  • ae57cdc691 Improve the debug messages when invalid instructions are found taitep 2025-12-22 19:57:33 +01:00
  • bac68d7118 Pull out memory access instructions from rvi.rs to their own file taitep 2025-12-22 19:51:21 +01:00
  • 8cce960b29 Implement SW taitep 2025-12-22 19:44:37 +01:00
  • cb100e92ac Implement SUB taitep 2025-12-22 19:33:40 +01:00
  • d0d3775b88 Implement OR taitep 2025-12-22 19:29:31 +01:00
  • 1ddda6614a Implement AND and improve formatting and ordering in rvi.rs taitep 2025-12-22 19:25:19 +01:00
  • ff161a69e6 Implement ADD taitep 2025-12-22 19:19:19 +01:00
  • e00103375d Fix page offset miscalculation in instruction fetch taitep 2025-12-22 18:28:31 +01:00
  • 7177633477 WHY WAS I USING S-TYPE IMMEDIATE IN LD (also add some more debugging info on an exception) taitep 2025-12-22 18:00:15 +01:00
  • 48477bd8b1 Make echo.S compatible with the C-compatible linker script taitep 2025-12-21 22:51:29 +01:00
  • 24dcf5d5bd Improve UART by using nonblocking stdin taitep 2025-12-21 21:25:29 +01:00
  • 209e44ae64 Implement LD and BNE taitep 2025-12-21 21:00:25 +01:00
  • 5b2d6a1af0 Fix memory size in link.ld taitep 2025-12-21 20:04:06 +01:00
  • a2d4dec417 Add some stuff to help with using C in link.ld taitep 2025-12-21 19:38:32 +01:00
  • 6c39a5eef2 Implement JALR, fix JAL, change how some stuff in instructions.rs is expressed taitep 2025-12-21 19:36:25 +01:00
  • 944ed573c6 Switch the current binary to use anyhow errors and add a proper argument number check taitep 2025-12-21 19:06:23 +01:00
  • 2e1c0a7dce Implement AUIPC taitep 2025-12-21 19:01:02 +01:00
  • 5c132b55e9 Fix assembly syntax in echo program taitep 2025-12-21 17:56:40 +01:00
  • c10e1ec09b Allow other image file names through cli args, increase ram size, update readme taitep 2025-12-21 17:49:02 +01:00
  • 25dd685345 Add a linker script and example uart echo program taitep 2025-12-21 17:04:18 +01:00
  • c05ba60c3c Implement ANDI and BEQ taitep 2025-12-21 16:29:28 +01:00
  • acc267a460 Remove unused imports from the UART implementation taitep 2025-12-21 16:01:39 +01:00
  • 25c3b9f5e2 Make a dedicated function for advancing the PC by one instruction taitep 2025-12-21 16:00:54 +01:00
  • 390a2b3228 Implement LB and LBU taitep 2025-12-21 15:56:50 +01:00
  • 25ecfca912 Make the UART not constantly flush output taitep 2025-12-21 15:45:32 +01:00
  • 0457530e0c Add a basic UART (very much temporary, its performance is most likely horrible taitep 2025-12-21 15:27:39 +01:00
  • eec40b069a Implement SB taitep 2025-12-21 14:24:20 +01:00
  • e910036058 Fix sd address calculation taitep 2025-12-21 14:08:06 +01:00
  • 049334ebdb Remove a debug print from SLLI taitep 2025-12-21 14:02:20 +01:00
  • d03863f5a2 Implement SLLI and fix sign extension of immediates for I-type and S-type instructions taitep 2025-12-21 14:00:47 +01:00
  • 87e6d03dbd Set version to 0.0.0 taitep 2025-12-21 13:09:10 +01:00
  • 00976cb7cd Add some stuff to the readme taitep 2025-12-21 13:03:18 +01:00
  • e8da0fc396 Get rid of some useless warnings in main.rs taitep 2025-12-21 12:56:22 +01:00
  • 62c6f905ce Remove unneeded once_cell dependency taitep 2025-12-21 12:49:15 +01:00
  • c74b4a21d2 Add decode functions for immediate shifts (funct6 and imm_shamt), make decode functions not use references, add inline hints to decode functions taitep 2025-12-21 12:47:56 +01:00
  • 23647ae966 Add JAL and change some of the formatting on previous instructions to be cleaner taitep 2025-12-21 12:20:30 +01:00
  • ac9506a1a7 (BIG CHANGE) Switch instruction identification/execution to use a plain match tree, should improve performance by quite a bit taitep 2025-12-21 12:07:12 +01:00
  • e2d521bbe7 Add license/copyright notices to top of each source file (where applicable) taitep 2025-12-01 22:06:13 +01:00
  • 6b49b34cc5 rename to TRVE taitep 2025-11-18 20:58:49 +01:00
  • 9c4e2d17a2 Add support for addiw and lui taitep 2025-10-21 14:46:02 +02:00
  • 19568f855e Add a todo taitep 2025-10-14 18:22:09 +02:00
  • 7a519924cb Move funct3 values to rvi.rs instead of being in opcodes.rs taitep 2025-10-14 18:21:28 +02:00
  • 6bd31e73fb some debugging stuff and SECOND OPCODE! taitep 2025-10-10 19:01:04 +02:00
  • bf5562df54 Make fields of DeviceEntry public taitep 2025-10-09 20:27:20 +02:00
  • 5274828b81 Make some constants and type aliases public taitep 2025-10-09 20:26:09 +02:00
  • ee5f5a2ec4 FIRST INSTRUCTION WORKING taitep 2025-10-07 20:23:59 +02:00
  • 361b36fbd1 Make sure unsupported/illegal instructions are caught taitep 2025-10-07 20:16:27 +02:00
  • dbd022f9c9 Make fields and register access functions of Core accessible to the rest of the emulator taitep 2025-10-07 20:12:09 +02:00
  • 908be749ac Make fields of MemConfig public to allow creating one taitep 2025-10-07 17:04:20 +02:00