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7a22570a0f
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Improve the debug messages when invalid instructions are found (again)
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2025-12-22 22:46:45 +01:00 |
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2b5eb96187
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Implement BLTU
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2025-12-22 21:17:38 +01:00 |
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be1b1b9fe6
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Implement LH
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2025-12-22 21:15:24 +01:00 |
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5cbaf2dc66
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Implement BGEU
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2025-12-22 20:08:16 +01:00 |
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ae57cdc691
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Improve the debug messages when invalid instructions are found
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2025-12-22 19:57:33 +01:00 |
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bac68d7118
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Pull out memory access instructions from rvi.rs to their own file
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2025-12-22 19:51:21 +01:00 |
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8cce960b29
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Implement SW
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2025-12-22 19:44:37 +01:00 |
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cb100e92ac
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Implement SUB
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2025-12-22 19:33:40 +01:00 |
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d0d3775b88
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Implement OR
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2025-12-22 19:29:31 +01:00 |
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1ddda6614a
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Implement AND and improve formatting and ordering in rvi.rs
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2025-12-22 19:25:19 +01:00 |
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ff161a69e6
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Implement ADD
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2025-12-22 19:19:19 +01:00 |
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e00103375d
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Fix page offset miscalculation in instruction fetch
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2025-12-22 18:28:31 +01:00 |
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7177633477
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WHY WAS I USING S-TYPE IMMEDIATE IN LD (also add some more debugging info on an exception)
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2025-12-22 18:00:15 +01:00 |
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24dcf5d5bd
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Improve UART by using nonblocking stdin
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2025-12-21 21:25:29 +01:00 |
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209e44ae64
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Implement LD and BNE
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2025-12-21 21:00:25 +01:00 |
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6c39a5eef2
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Implement JALR, fix JAL, change how some stuff in instructions.rs is expressed
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2025-12-21 19:36:25 +01:00 |
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944ed573c6
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Switch the current binary to use anyhow errors and add a proper argument number check
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2025-12-21 19:06:23 +01:00 |
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2e1c0a7dce
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Implement AUIPC
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2025-12-21 19:01:02 +01:00 |
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c10e1ec09b
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Allow other image file names through cli args, increase ram size, update readme
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2025-12-21 17:49:02 +01:00 |
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c05ba60c3c
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Implement ANDI and BEQ
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2025-12-21 16:29:28 +01:00 |
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acc267a460
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Remove unused imports from the UART implementation
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2025-12-21 16:01:39 +01:00 |
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25c3b9f5e2
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Make a dedicated function for advancing the PC by one instruction
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2025-12-21 16:00:54 +01:00 |
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390a2b3228
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Implement LB and LBU
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2025-12-21 15:56:50 +01:00 |
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25ecfca912
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Make the UART not constantly flush output
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2025-12-21 15:45:32 +01:00 |
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0457530e0c
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Add a basic UART (very much temporary, its performance is most likely horrible
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2025-12-21 15:27:39 +01:00 |
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eec40b069a
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Implement SB
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2025-12-21 14:24:20 +01:00 |
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e910036058
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Fix sd address calculation
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2025-12-21 14:08:06 +01:00 |
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049334ebdb
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Remove a debug print from SLLI
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2025-12-21 14:02:20 +01:00 |
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d03863f5a2
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Implement SLLI and fix sign extension of immediates for I-type and S-type instructions
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2025-12-21 14:00:47 +01:00 |
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e8da0fc396
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Get rid of some useless warnings in main.rs
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2025-12-21 12:56:22 +01:00 |
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c74b4a21d2
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Add decode functions for immediate shifts (funct6 and imm_shamt), make decode functions not use references, add inline hints to decode functions
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2025-12-21 12:47:56 +01:00 |
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23647ae966
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Add JAL and change some of the formatting on previous instructions to be cleaner
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2025-12-21 12:20:30 +01:00 |
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ac9506a1a7
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(BIG CHANGE) Switch instruction identification/execution to use a plain match tree, should improve performance by quite a bit
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2025-12-21 12:07:12 +01:00 |
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e2d521bbe7
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Add license/copyright notices to top of each source file (where applicable)
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2025-12-01 22:06:13 +01:00 |
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6b49b34cc5
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rename to TRVE
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2025-11-18 20:58:49 +01:00 |
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9c4e2d17a2
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Add support for addiw and lui
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2025-10-21 14:46:02 +02:00 |
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19568f855e
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Add a todo
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2025-10-14 18:22:09 +02:00 |
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7a519924cb
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Move funct3 values to rvi.rs instead of being in opcodes.rs
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2025-10-14 18:21:28 +02:00 |
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6bd31e73fb
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some debugging stuff and SECOND OPCODE!
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2025-10-10 19:01:04 +02:00 |
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bf5562df54
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Make fields of DeviceEntry public
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2025-10-09 20:27:20 +02:00 |
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5274828b81
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Make some constants and type aliases public
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2025-10-09 20:26:09 +02:00 |
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ee5f5a2ec4
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FIRST INSTRUCTION WORKING
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2025-10-07 20:23:59 +02:00 |
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361b36fbd1
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Make sure unsupported/illegal instructions are caught
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2025-10-07 20:16:27 +02:00 |
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dbd022f9c9
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Make fields and register access functions of Core accessible to the rest of the emulator
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2025-10-07 20:12:09 +02:00 |
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908be749ac
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Make fields of MemConfig public to allow creating one
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2025-10-07 17:04:20 +02:00 |
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52952840aa
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I guess its a working execution loop?
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2025-10-04 14:07:42 +02:00 |
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bb0007707c
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Swap out execution status for instructions returning an InstructionResult
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2025-10-03 13:28:02 +02:00 |
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4632fe29ce
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Initial instruction execution code i guess
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2025-09-30 18:39:14 +02:00 |
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f5ac1a132f
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Allow identification of the type of memory (ram or mmio) backing a specific page
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2025-09-28 21:13:29 +02:00 |
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3163b43fa4
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base core state & instruction decoder
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2025-09-27 21:43:10 +02:00 |
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