35 lines
1.4 KiB
Markdown
35 lines
1.4 KiB
Markdown
# trve
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taitep's RISC-V Emulator.
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The goal is to support at least RV64GC and be able to run Linux,
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potentially more. No plans for RV32I or RV32/64E.
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Currently implemented RISC-V ISA: `RV64IM-Zalrsc`
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## Current Use
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Currently, the emulator is nowhere near complete,
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its not even at rv64i, but it does work for a subset of it.
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The emulator will load a raw binary image or static ELF executable from a file specified as a CLI argument into RAM,
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which starts at 0x80000000 and is currently 16MiB,
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and start execution at the start of the image/ram or the ELF entry point.
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It also starts a gdb stub/server listening on localhost:1234. By giving the command line argument
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`--wait`, you can make execution wait until GDB is connected, allowing you to follow execution
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from the start.
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There is also a debug out section at `0x00000000`-`0x00010000`.
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Anything written to it will be logged out in hex.
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There is also a UART at `0x00010000`-`0x00010002`, the interface is quite simple:
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- byte `0`: Data. When written, writes out the character
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When read, reads a character from the buffer, or 0 if empty.
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- byte `1`: Status. Read-only. Least significant bit is `TX_READY` and indicates whether
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the UART is ready to be written to. Currently always 1.
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Next least significant is `RX_READY`, indicates whether the read buffer
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has any data to read.
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## Licensing
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This project is licensed under the BSD 2-Clause license.
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See the LICENSE file in the project root
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