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taitep 6bd31e73fb some debugging stuff and SECOND OPCODE!
2025-10-10 19:01:04 +02:00
src
some debugging stuff and SECOND OPCODE!
2025-10-10 19:01:04 +02:00
.gitignore
Initial stuff and memory implementation
2025-09-27 16:38:06 +02:00
Cargo.lock
Initial instruction execution code i guess
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Cargo.toml
Initial instruction execution code i guess
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LICENSE
Initial commit
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README.md
Initial Readme
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README.md

rvem

RISC-V Emulator. The goal is to support at least RV64GC and be able to run Linux, potentially more. No plans for RV32I or RV32/64E.

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Description
taitep's RISC-V Emulator
Readme MIT 52 KiB
Languages
Rust 100%