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taitep 3163b43fa4 base core state & instruction decoder
2025-09-27 21:43:10 +02:00
src
base core state & instruction decoder
2025-09-27 21:43:10 +02:00
.gitignore
Initial stuff and memory implementation
2025-09-27 16:38:06 +02:00
Cargo.lock
Initial stuff and memory implementation
2025-09-27 16:38:06 +02:00
Cargo.toml
Initial stuff and memory implementation
2025-09-27 16:38:06 +02:00
LICENSE
Initial commit
2025-09-06 12:38:12 +02:00
README.md
Initial Readme
2025-09-27 16:37:41 +02:00

README.md

rvem

RISC-V Emulator. The goal is to support at least RV64GC and be able to run Linux, potentially more. No plans for RV32I or RV32/64E.

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Description
taitep's RISC-V Emulator
Readme MIT 52 KiB
Languages
Rust 100%