132 lines
3.9 KiB
Rust
132 lines
3.9 KiB
Rust
// Copyright (c) 2025 taitep
|
|
// SPDX-License-Identifier: BSD-2-Clause
|
|
//
|
|
// This file is part of TRVE (https://gitea.taitep.se/taitep/trve)
|
|
// See LICENSE file in the project root for full license text.
|
|
|
|
use crate::{core::Core, exceptions::Exception, instructions::Instruction};
|
|
|
|
pub fn sd(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
|
|
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
|
|
let value = core.reg_read(instr.rs2());
|
|
core.mem
|
|
.write_dword(addr, value)
|
|
.map_err(|e| e.into_exception_store())?;
|
|
core.advance_pc();
|
|
Ok(())
|
|
}
|
|
|
|
pub fn ld(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
|
|
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
|
|
core.reg_write(
|
|
instr.rd(),
|
|
core.mem
|
|
.read_dword(addr)
|
|
.map_err(|e| e.into_exception_load())?,
|
|
);
|
|
core.advance_pc();
|
|
Ok(())
|
|
}
|
|
|
|
pub fn sw(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
|
|
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
|
|
let value = core.reg_read(instr.rs2()) as u32;
|
|
core.mem
|
|
.write_word(addr, value)
|
|
.map_err(|e| e.into_exception_store())?;
|
|
core.advance_pc();
|
|
Ok(())
|
|
}
|
|
|
|
pub fn lw(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
|
|
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
|
|
core.reg_write(
|
|
instr.rd(),
|
|
core.mem
|
|
.read_word(addr)
|
|
.map_err(|e| e.into_exception_load())? as i32 as i64 as u64,
|
|
);
|
|
core.advance_pc();
|
|
Ok(())
|
|
}
|
|
|
|
pub fn lwu(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
|
|
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
|
|
core.reg_write(
|
|
instr.rd(),
|
|
core.mem
|
|
.read_word(addr)
|
|
.map_err(|e| e.into_exception_load())? as u64,
|
|
);
|
|
core.advance_pc();
|
|
Ok(())
|
|
}
|
|
|
|
pub fn sh(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
|
|
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
|
|
let value = core.reg_read(instr.rs2()) as u16;
|
|
core.mem
|
|
.write_hword(addr, value)
|
|
.map_err(|e| e.into_exception_store())?;
|
|
core.advance_pc();
|
|
Ok(())
|
|
}
|
|
|
|
pub fn lh(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
|
|
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
|
|
core.reg_write(
|
|
instr.rd(),
|
|
core.mem
|
|
.read_hword(addr)
|
|
.map_err(|e| e.into_exception_load())? as i16 as i64 as u64,
|
|
);
|
|
core.advance_pc();
|
|
Ok(())
|
|
}
|
|
|
|
pub fn lhu(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
|
|
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
|
|
core.reg_write(
|
|
instr.rd(),
|
|
core.mem
|
|
.read_hword(addr)
|
|
.map_err(|e| e.into_exception_load())? as u64,
|
|
);
|
|
core.advance_pc();
|
|
Ok(())
|
|
}
|
|
|
|
pub fn sb(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
|
|
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
|
|
let value = core.reg_read(instr.rs2()) as u8;
|
|
core.mem
|
|
.write_byte(addr, value)
|
|
.map_err(|e| e.into_exception_store())?;
|
|
core.advance_pc();
|
|
Ok(())
|
|
}
|
|
|
|
pub fn lb(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
|
|
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
|
|
core.reg_write(
|
|
instr.rd(),
|
|
core.mem
|
|
.read_byte(addr)
|
|
.map_err(|e| e.into_exception_load())? as i8 as i64 as u64,
|
|
);
|
|
core.advance_pc();
|
|
Ok(())
|
|
}
|
|
|
|
pub fn lbu(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
|
|
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
|
|
core.reg_write(
|
|
instr.rd(),
|
|
core.mem
|
|
.read_byte(addr)
|
|
.map_err(|e| e.into_exception_load())? as u64,
|
|
);
|
|
core.advance_pc();
|
|
Ok(())
|
|
}
|