|
|
d3e8af85a6
|
Add the files and decode logic for RVA
|
2026-01-12 17:25:02 +01:00 |
|
|
|
0f0e844223
|
Finish RV64M
|
2025-12-30 20:53:57 +01:00 |
|
|
|
5a383956c9
|
Improve exception dumps and general debug info, make the emulator capable of running the riscv ISA tests, and perform some general fixes i found while making it pass the tests for RV64I
|
2025-12-30 20:18:23 +01:00 |
|
|
|
6a0e5e63c1
|
Implement DIV
|
2025-12-30 17:27:42 +01:00 |
|
|
|
e5c5312566
|
Implement MUL
|
2025-12-30 16:56:09 +01:00 |
|
|
|
9a9bef7dd7
|
Remove consts.rs and just use plain types
|
2025-12-28 12:01:39 +01:00 |
|
|
|
8024af6b13
|
Implement ECALL and EBREAK, the final RV64I instructions!
|
2025-12-27 21:47:22 +01:00 |
|
|
|
5c008bfc04
|
Add exception values (what will go in mtval/stval)
|
2025-12-27 21:33:39 +01:00 |
|
|
|
b5d36b7969
|
Initial FENCE implementation
|
2025-12-27 21:03:24 +01:00 |
|
|
|
6a3920895b
|
Relicense to BSD 2-Clause to align better with the RISC-V community
|
2025-12-27 12:44:55 +01:00 |
|
|
|
34034dd5db
|
Make macros for R/I-type operations and use them to implement basically every single one i think
|
2025-12-26 18:14:32 +01:00 |
|
|
|
75e843f5f9
|
Make branches macros and implement all of them
|
2025-12-26 16:06:30 +01:00 |
|
|
|
528b519ce9
|
(BIG CHANGE) memory handling has changed, MMIO is now a 2 level page table, misaligned access supported, addresses not internally split to page and offset immediately, all load/store instructions implemented. Might still have bugs
|
2025-12-26 14:20:27 +01:00 |
|
|
|
09d9064372
|
EXCEPTION SYSTEM (initial version - may change later)
|
2025-12-24 13:56:41 +01:00 |
|
|
|
0c6a540a85
|
Implement SRLI
|
2025-12-23 18:42:50 +01:00 |
|
|
|
23392a55df
|
Implement SH
|
2025-12-23 18:31:04 +01:00 |
|
|
|
c6da147d50
|
Implement BLT
|
2025-12-23 09:51:53 +01:00 |
|
|
|
0ac363e203
|
Implement LW
|
2025-12-22 22:48:57 +01:00 |
|
|
|
2b5eb96187
|
Implement BLTU
|
2025-12-22 21:17:38 +01:00 |
|
|
|
be1b1b9fe6
|
Implement LH
|
2025-12-22 21:15:24 +01:00 |
|
|
|
5cbaf2dc66
|
Implement BGEU
|
2025-12-22 20:08:16 +01:00 |
|
|
|
8cce960b29
|
Implement SW
|
2025-12-22 19:44:37 +01:00 |
|
|
|
cb100e92ac
|
Implement SUB
|
2025-12-22 19:33:40 +01:00 |
|
|
|
d0d3775b88
|
Implement OR
|
2025-12-22 19:29:31 +01:00 |
|
|
|
1ddda6614a
|
Implement AND and improve formatting and ordering in rvi.rs
|
2025-12-22 19:25:19 +01:00 |
|
|
|
ff161a69e6
|
Implement ADD
|
2025-12-22 19:19:19 +01:00 |
|
|
|
209e44ae64
|
Implement LD and BNE
|
2025-12-21 21:00:25 +01:00 |
|
|
|
6c39a5eef2
|
Implement JALR, fix JAL, change how some stuff in instructions.rs is expressed
|
2025-12-21 19:36:25 +01:00 |
|
|
|
2e1c0a7dce
|
Implement AUIPC
|
2025-12-21 19:01:02 +01:00 |
|
|
|
c05ba60c3c
|
Implement ANDI and BEQ
|
2025-12-21 16:29:28 +01:00 |
|
|
|
390a2b3228
|
Implement LB and LBU
|
2025-12-21 15:56:50 +01:00 |
|
|
|
eec40b069a
|
Implement SB
|
2025-12-21 14:24:20 +01:00 |
|
|
|
d03863f5a2
|
Implement SLLI and fix sign extension of immediates for I-type and S-type instructions
|
2025-12-21 14:00:47 +01:00 |
|
|
|
23647ae966
|
Add JAL and change some of the formatting on previous instructions to be cleaner
|
2025-12-21 12:20:30 +01:00 |
|
|
|
ac9506a1a7
|
(BIG CHANGE) Switch instruction identification/execution to use a plain match tree, should improve performance by quite a bit
|
2025-12-21 12:07:12 +01:00 |
|
|
|
e2d521bbe7
|
Add license/copyright notices to top of each source file (where applicable)
|
2025-12-01 22:06:13 +01:00 |
|
|
|
ee5f5a2ec4
|
FIRST INSTRUCTION WORKING
|
2025-10-07 20:23:59 +02:00 |
|
|
|
52952840aa
|
I guess its a working execution loop?
|
2025-10-04 14:07:42 +02:00 |
|
|
|
bb0007707c
|
Swap out execution status for instructions returning an InstructionResult
|
2025-10-03 13:28:02 +02:00 |
|
|
|
4632fe29ce
|
Initial instruction execution code i guess
|
2025-09-30 18:39:14 +02:00 |
|
