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6a0e5e63c1
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Implement DIV
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2025-12-30 17:27:42 +01:00 |
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e5c5312566
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Implement MUL
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2025-12-30 16:56:09 +01:00 |
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9a9bef7dd7
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Remove consts.rs and just use plain types
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2025-12-28 12:01:39 +01:00 |
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5c008bfc04
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Add exception values (what will go in mtval/stval)
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2025-12-27 21:33:39 +01:00 |
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6a3920895b
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Relicense to BSD 2-Clause to align better with the RISC-V community
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2025-12-27 12:44:55 +01:00 |
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34034dd5db
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Make macros for R/I-type operations and use them to implement basically every single one i think
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2025-12-26 18:14:32 +01:00 |
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75e843f5f9
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Make branches macros and implement all of them
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2025-12-26 16:06:30 +01:00 |
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528b519ce9
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(BIG CHANGE) memory handling has changed, MMIO is now a 2 level page table, misaligned access supported, addresses not internally split to page and offset immediately, all load/store instructions implemented. Might still have bugs
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2025-12-26 14:20:27 +01:00 |
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09d9064372
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EXCEPTION SYSTEM (initial version - may change later)
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2025-12-24 13:56:41 +01:00 |
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36faa1e39c
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Add license headers to files missing them
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2025-12-23 19:22:11 +01:00 |
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0c6a540a85
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Implement SRLI
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2025-12-23 18:42:50 +01:00 |
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23392a55df
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Implement SH
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2025-12-23 18:31:04 +01:00 |
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f38114dbd7
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Remove some debug messages i forgot
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2025-12-23 11:01:28 +01:00 |
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c6da147d50
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Implement BLT
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2025-12-23 09:51:53 +01:00 |
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0ac363e203
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Implement LW
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2025-12-22 22:48:57 +01:00 |
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2b5eb96187
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Implement BLTU
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2025-12-22 21:17:38 +01:00 |
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be1b1b9fe6
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Implement LH
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2025-12-22 21:15:24 +01:00 |
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5cbaf2dc66
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Implement BGEU
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2025-12-22 20:08:16 +01:00 |
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bac68d7118
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Pull out memory access instructions from rvi.rs to their own file
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2025-12-22 19:51:21 +01:00 |
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8cce960b29
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Implement SW
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2025-12-22 19:44:37 +01:00 |
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cb100e92ac
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Implement SUB
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2025-12-22 19:33:40 +01:00 |
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d0d3775b88
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Implement OR
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2025-12-22 19:29:31 +01:00 |
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1ddda6614a
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Implement AND and improve formatting and ordering in rvi.rs
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2025-12-22 19:25:19 +01:00 |
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ff161a69e6
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Implement ADD
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2025-12-22 19:19:19 +01:00 |
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7177633477
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WHY WAS I USING S-TYPE IMMEDIATE IN LD (also add some more debugging info on an exception)
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2025-12-22 18:00:15 +01:00 |
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209e44ae64
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Implement LD and BNE
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2025-12-21 21:00:25 +01:00 |
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6c39a5eef2
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Implement JALR, fix JAL, change how some stuff in instructions.rs is expressed
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2025-12-21 19:36:25 +01:00 |
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2e1c0a7dce
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Implement AUIPC
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2025-12-21 19:01:02 +01:00 |
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c05ba60c3c
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Implement ANDI and BEQ
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2025-12-21 16:29:28 +01:00 |
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25c3b9f5e2
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Make a dedicated function for advancing the PC by one instruction
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2025-12-21 16:00:54 +01:00 |
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390a2b3228
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Implement LB and LBU
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2025-12-21 15:56:50 +01:00 |
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eec40b069a
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Implement SB
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2025-12-21 14:24:20 +01:00 |
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e910036058
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Fix sd address calculation
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2025-12-21 14:08:06 +01:00 |
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049334ebdb
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Remove a debug print from SLLI
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2025-12-21 14:02:20 +01:00 |
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d03863f5a2
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Implement SLLI and fix sign extension of immediates for I-type and S-type instructions
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2025-12-21 14:00:47 +01:00 |
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23647ae966
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Add JAL and change some of the formatting on previous instructions to be cleaner
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2025-12-21 12:20:30 +01:00 |
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ac9506a1a7
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(BIG CHANGE) Switch instruction identification/execution to use a plain match tree, should improve performance by quite a bit
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2025-12-21 12:07:12 +01:00 |
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e2d521bbe7
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Add license/copyright notices to top of each source file (where applicable)
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2025-12-01 22:06:13 +01:00 |
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9c4e2d17a2
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Add support for addiw and lui
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2025-10-21 14:46:02 +02:00 |
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19568f855e
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Add a todo
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2025-10-14 18:22:09 +02:00 |
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7a519924cb
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Move funct3 values to rvi.rs instead of being in opcodes.rs
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2025-10-14 18:21:28 +02:00 |
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6bd31e73fb
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some debugging stuff and SECOND OPCODE!
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2025-10-10 19:01:04 +02:00 |
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ee5f5a2ec4
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FIRST INSTRUCTION WORKING
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2025-10-07 20:23:59 +02:00 |
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