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5a383956c9
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Improve exception dumps and general debug info, make the emulator capable of running the riscv ISA tests, and perform some general fixes i found while making it pass the tests for RV64I
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2025-12-30 20:18:23 +01:00 |
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9a9bef7dd7
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Remove consts.rs and just use plain types
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2025-12-28 12:01:39 +01:00 |
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5c008bfc04
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Add exception values (what will go in mtval/stval)
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2025-12-27 21:33:39 +01:00 |
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970c1adcb0
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Add checks to make sure that ram has a size that is a multiple of 8
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2025-12-27 20:52:32 +01:00 |
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6a3920895b
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Relicense to BSD 2-Clause to align better with the RISC-V community
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2025-12-27 12:44:55 +01:00 |
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528b519ce9
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(BIG CHANGE) memory handling has changed, MMIO is now a 2 level page table, misaligned access supported, addresses not internally split to page and offset immediately, all load/store instructions implemented. Might still have bugs
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2025-12-26 14:20:27 +01:00 |
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66c63ab63c
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Add a default implementation for the memory device interface that just returns access faults
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2025-12-24 14:06:16 +01:00 |
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09d9064372
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EXCEPTION SYSTEM (initial version - may change later)
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2025-12-24 13:56:41 +01:00 |
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e2d521bbe7
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Add license/copyright notices to top of each source file (where applicable)
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2025-12-01 22:06:13 +01:00 |
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bf5562df54
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Make fields of DeviceEntry public
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2025-10-09 20:27:20 +02:00 |
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5274828b81
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Make some constants and type aliases public
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2025-10-09 20:26:09 +02:00 |
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908be749ac
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Make fields of MemConfig public to allow creating one
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2025-10-07 17:04:20 +02:00 |
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f5ac1a132f
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Allow identification of the type of memory (ram or mmio) backing a specific page
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2025-09-28 21:13:29 +02:00 |
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5919041f07
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actually no NOW the memory interface is "done"
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2025-09-27 17:48:56 +02:00 |
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4a2272ae49
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Initial stuff and memory implementation
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2025-09-27 16:38:06 +02:00 |
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