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5a383956c9
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Improve exception dumps and general debug info, make the emulator capable of running the riscv ISA tests, and perform some general fixes i found while making it pass the tests for RV64I
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2025-12-30 20:18:23 +01:00 |
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9a9bef7dd7
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Remove consts.rs and just use plain types
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2025-12-28 12:01:39 +01:00 |
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8024af6b13
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Implement ECALL and EBREAK, the final RV64I instructions!
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2025-12-27 21:47:22 +01:00 |
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6a3920895b
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Relicense to BSD 2-Clause to align better with the RISC-V community
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2025-12-27 12:44:55 +01:00 |
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9f8e9ec380
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Implement a GDB stub and fix another huge issue in S-type immediate decoding
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2025-12-27 11:48:36 +01:00 |
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34034dd5db
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Make macros for R/I-type operations and use them to implement basically every single one i think
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2025-12-26 18:14:32 +01:00 |
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643a39c24a
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Fix s-type immediate decoding
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2025-12-23 09:51:32 +01:00 |
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d03863f5a2
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Implement SLLI and fix sign extension of immediates for I-type and S-type instructions
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2025-12-21 14:00:47 +01:00 |
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c74b4a21d2
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Add decode functions for immediate shifts (funct6 and imm_shamt), make decode functions not use references, add inline hints to decode functions
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2025-12-21 12:47:56 +01:00 |
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e2d521bbe7
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Add license/copyright notices to top of each source file (where applicable)
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2025-12-01 22:06:13 +01:00 |
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361b36fbd1
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Make sure unsupported/illegal instructions are caught
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2025-10-07 20:16:27 +02:00 |
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52952840aa
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I guess its a working execution loop?
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2025-10-04 14:07:42 +02:00 |
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3163b43fa4
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base core state & instruction decoder
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2025-09-27 21:43:10 +02:00 |
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