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5a383956c9
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Improve exception dumps and general debug info, make the emulator capable of running the riscv ISA tests, and perform some general fixes i found while making it pass the tests for RV64I
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2025-12-30 20:18:23 +01:00 |
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9a9bef7dd7
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Remove consts.rs and just use plain types
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2025-12-28 12:01:39 +01:00 |
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5c008bfc04
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Add exception values (what will go in mtval/stval)
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2025-12-27 21:33:39 +01:00 |
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6a3920895b
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Relicense to BSD 2-Clause to align better with the RISC-V community
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2025-12-27 12:44:55 +01:00 |
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67406a9c48
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Fix some warnings
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2025-12-27 11:55:19 +01:00 |
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9f8e9ec380
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Implement a GDB stub and fix another huge issue in S-type immediate decoding
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2025-12-27 11:48:36 +01:00 |
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34034dd5db
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Make macros for R/I-type operations and use them to implement basically every single one i think
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2025-12-26 18:14:32 +01:00 |
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528b519ce9
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(BIG CHANGE) memory handling has changed, MMIO is now a 2 level page table, misaligned access supported, addresses not internally split to page and offset immediately, all load/store instructions implemented. Might still have bugs
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2025-12-26 14:20:27 +01:00 |
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6d9efb7eb8
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Small refactor in exception handling in core.rs
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2025-12-24 16:14:54 +01:00 |
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09d9064372
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EXCEPTION SYSTEM (initial version - may change later)
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2025-12-24 13:56:41 +01:00 |
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43bae12ea0
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Comment out the unused 'Pause' instruction result
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2025-12-23 18:46:38 +01:00 |
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1b409cd14e
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Improve error messaging
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2025-12-23 09:51:09 +01:00 |
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7a22570a0f
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Improve the debug messages when invalid instructions are found (again)
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2025-12-22 22:46:45 +01:00 |
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ae57cdc691
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Improve the debug messages when invalid instructions are found
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2025-12-22 19:57:33 +01:00 |
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e00103375d
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Fix page offset miscalculation in instruction fetch
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2025-12-22 18:28:31 +01:00 |
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7177633477
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WHY WAS I USING S-TYPE IMMEDIATE IN LD (also add some more debugging info on an exception)
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2025-12-22 18:00:15 +01:00 |
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25c3b9f5e2
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Make a dedicated function for advancing the PC by one instruction
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2025-12-21 16:00:54 +01:00 |
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ac9506a1a7
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(BIG CHANGE) Switch instruction identification/execution to use a plain match tree, should improve performance by quite a bit
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2025-12-21 12:07:12 +01:00 |
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e2d521bbe7
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Add license/copyright notices to top of each source file (where applicable)
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2025-12-01 22:06:13 +01:00 |
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6bd31e73fb
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some debugging stuff and SECOND OPCODE!
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2025-10-10 19:01:04 +02:00 |
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361b36fbd1
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Make sure unsupported/illegal instructions are caught
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2025-10-07 20:16:27 +02:00 |
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dbd022f9c9
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Make fields and register access functions of Core accessible to the rest of the emulator
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2025-10-07 20:12:09 +02:00 |
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52952840aa
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I guess its a working execution loop?
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2025-10-04 14:07:42 +02:00 |
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bb0007707c
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Swap out execution status for instructions returning an InstructionResult
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2025-10-03 13:28:02 +02:00 |
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3163b43fa4
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base core state & instruction decoder
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2025-09-27 21:43:10 +02:00 |
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