Logo
Explore Help
Sign In
taitep/trve
1
1
Fork 0
You've already forked trve
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
80 Commits 1 Branch 0 Tags
528b519ce98c21049705526442cbde1672495b49
Commit Graph

7 Commits

Author SHA1 Message Date
taitep
528b519ce9 (BIG CHANGE) memory handling has changed, MMIO is now a 2 level page table, misaligned access supported, addresses not internally split to page and offset immediately, all load/store instructions implemented. Might still have bugs 2025-12-26 14:20:27 +01:00
taitep
09d9064372 EXCEPTION SYSTEM (initial version - may change later) 2025-12-24 13:56:41 +01:00
taitep
36faa1e39c Add license headers to files missing them 2025-12-23 19:22:11 +01:00
taitep
24dcf5d5bd Improve UART by using nonblocking stdin 2025-12-21 21:25:29 +01:00
taitep
acc267a460 Remove unused imports from the UART implementation 2025-12-21 16:01:39 +01:00
taitep
25ecfca912 Make the UART not constantly flush output 2025-12-21 15:45:32 +01:00
taitep
0457530e0c Add a basic UART (very much temporary, its performance is most likely horrible 2025-12-21 15:27:39 +01:00
Powered by Gitea Version: 1.25.2 Page: 39ms Template: 5ms
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API