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21fb6cbc8b
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Switch from std::mpsc channels to crossbeam
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2026-01-02 12:44:50 +01:00 |
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bbc9e0b9ff
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2026! Updating LICENSE file now and individual file comments when those files are updated
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2026-01-01 09:15:25 +01:00 |
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7fcfc031ef
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Stop rust-analyzer from complaining about the big endian host error
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2025-12-31 13:19:04 +01:00 |
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21a8479ce9
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Make MMIO devices not have control of the address of exceptions
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2025-12-31 13:16:32 +01:00 |
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09fe12f516
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Change some ordering in core.rs and deduplicate core command handling
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2025-12-31 09:33:14 +01:00 |
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0f0e844223
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Finish RV64M
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2025-12-30 20:53:57 +01:00 |
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5a383956c9
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Improve exception dumps and general debug info, make the emulator capable of running the riscv ISA tests, and perform some general fixes i found while making it pass the tests for RV64I
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2025-12-30 20:18:23 +01:00 |
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6a0e5e63c1
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Implement DIV
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2025-12-30 17:27:42 +01:00 |
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e5c5312566
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Implement MUL
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2025-12-30 16:56:09 +01:00 |
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9a9bef7dd7
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Remove consts.rs and just use plain types
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2025-12-28 12:01:39 +01:00 |
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8024af6b13
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Implement ECALL and EBREAK, the final RV64I instructions!
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2025-12-27 21:47:22 +01:00 |
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5c008bfc04
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Add exception values (what will go in mtval/stval)
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2025-12-27 21:33:39 +01:00 |
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b5d36b7969
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Initial FENCE implementation
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2025-12-27 21:03:24 +01:00 |
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970c1adcb0
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Add checks to make sure that ram has a size that is a multiple of 8
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2025-12-27 20:52:32 +01:00 |
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6a3920895b
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Relicense to BSD 2-Clause to align better with the RISC-V community
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2025-12-27 12:44:55 +01:00 |
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67406a9c48
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Fix some warnings
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2025-12-27 11:55:19 +01:00 |
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9f8e9ec380
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Implement a GDB stub and fix another huge issue in S-type immediate decoding
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2025-12-27 11:48:36 +01:00 |
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a64fcaa3b5
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Make execload respect the static ram start
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2025-12-26 19:32:55 +01:00 |
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34034dd5db
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Make macros for R/I-type operations and use them to implement basically every single one i think
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2025-12-26 18:14:32 +01:00 |
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75e843f5f9
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Make branches macros and implement all of them
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2025-12-26 16:06:30 +01:00 |
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528b519ce9
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(BIG CHANGE) memory handling has changed, MMIO is now a 2 level page table, misaligned access supported, addresses not internally split to page and offset immediately, all load/store instructions implemented. Might still have bugs
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2025-12-26 14:20:27 +01:00 |
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6d9efb7eb8
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Small refactor in exception handling in core.rs
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2025-12-24 16:14:54 +01:00 |
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44394b3d19
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Update README to mention ELF support
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2025-12-24 14:11:29 +01:00 |
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66c63ab63c
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Add a default implementation for the memory device interface that just returns access faults
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2025-12-24 14:06:16 +01:00 |
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09d9064372
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EXCEPTION SYSTEM (initial version - may change later)
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2025-12-24 13:56:41 +01:00 |
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3f789442c0
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some linker script updates to work even more properly for newlib i think
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2025-12-24 11:42:55 +01:00 |
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96c2cbf7ae
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remove unused imports in main.rs
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2025-12-23 20:04:14 +01:00 |
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8ed4845d58
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ADD ELF SUPPORT
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2025-12-23 19:56:42 +01:00 |
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36faa1e39c
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Add license headers to files missing them
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2025-12-23 19:22:11 +01:00 |
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43bae12ea0
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Comment out the unused 'Pause' instruction result
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2025-12-23 18:46:38 +01:00 |
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0c6a540a85
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Implement SRLI
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2025-12-23 18:42:50 +01:00 |
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23392a55df
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Implement SH
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2025-12-23 18:31:04 +01:00 |
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f38114dbd7
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Remove some debug messages i forgot
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2025-12-23 11:01:28 +01:00 |
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c6da147d50
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Implement BLT
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2025-12-23 09:51:53 +01:00 |
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643a39c24a
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Fix s-type immediate decoding
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2025-12-23 09:51:32 +01:00 |
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1b409cd14e
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Improve error messaging
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2025-12-23 09:51:09 +01:00 |
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976bd688b0
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Remove an unused import in main.rs
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2025-12-23 08:57:43 +01:00 |
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0ac363e203
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Implement LW
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2025-12-22 22:48:57 +01:00 |
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7a22570a0f
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Improve the debug messages when invalid instructions are found (again)
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2025-12-22 22:46:45 +01:00 |
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2b5eb96187
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Implement BLTU
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2025-12-22 21:17:38 +01:00 |
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be1b1b9fe6
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Implement LH
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2025-12-22 21:15:24 +01:00 |
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5cbaf2dc66
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Implement BGEU
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2025-12-22 20:08:16 +01:00 |
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ae57cdc691
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Improve the debug messages when invalid instructions are found
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2025-12-22 19:57:33 +01:00 |
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bac68d7118
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Pull out memory access instructions from rvi.rs to their own file
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2025-12-22 19:51:21 +01:00 |
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8cce960b29
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Implement SW
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2025-12-22 19:44:37 +01:00 |
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cb100e92ac
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Implement SUB
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2025-12-22 19:33:40 +01:00 |
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d0d3775b88
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Implement OR
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2025-12-22 19:29:31 +01:00 |
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1ddda6614a
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Implement AND and improve formatting and ordering in rvi.rs
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2025-12-22 19:25:19 +01:00 |
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ff161a69e6
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Implement ADD
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2025-12-22 19:19:19 +01:00 |
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e00103375d
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Fix page offset miscalculation in instruction fetch
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2025-12-22 18:28:31 +01:00 |
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