Implement OR

2025-12-22 19:29:31 +01:00
parent 1ddda6614a
commit d0d3775b88
2 changed files with 10 additions and 0 deletions
--- a/src/instructions/rvi.rs
+++ b/src/instructions/rvi.rs
@@ -52,6 +52,15 @@ pub fn andi(core: &mut Core, instr: Instruction) -> InstructionResult {
    InstructionResult::Normal
 }

+pub fn or(core: &mut Core, instr: Instruction) -> InstructionResult {
+    core.reg_write(
+        instr.rd(),
+        core.reg_read(instr.rs1()) | core.reg_read(instr.rs2()),
+    );
+    core.advance_pc();
+    InstructionResult::Normal
+}
+
 pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
    core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());
    core.advance_pc();