From d0d3775b888b6cf1e7d240d3426db4175c200b48 Mon Sep 17 00:00:00 2001
From: taitep <taitep@taitep.se>
Date: Mon, 22 Dec 2025 19:29:31 +0100
Subject: [PATCH] Implement OR

---
 src/instructions.rs     | 1 +
 src/instructions/rvi.rs | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/src/instructions.rs b/src/instructions.rs
index 3096ed0..6e9fbd8 100644
--- a/src/instructions.rs
+++ b/src/instructions.rs
@@ -17,6 +17,7 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Option<Instr
             // OP
             (0b0000000, 0b000) => Some(rvi::add(core, instr)),
             (0b0000000, 0b111) => Some(rvi::and(core, instr)),
+            (0b0000000, 0b110) => Some(rvi::or(core, instr)),
             _ => None,
         },
         0b00100 => match instr.funct3() {
diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs
index 395fe8e..69670d0 100644
--- a/src/instructions/rvi.rs
+++ b/src/instructions/rvi.rs
@@ -52,6 +52,15 @@ pub fn andi(core: &mut Core, instr: Instruction) -> InstructionResult {
     InstructionResult::Normal
 }
 
+pub fn or(core: &mut Core, instr: Instruction) -> InstructionResult {
+    core.reg_write(
+        instr.rd(),
+        core.reg_read(instr.rs1()) | core.reg_read(instr.rs2()),
+    );
+    core.advance_pc();
+    InstructionResult::Normal
+}
+
 pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
     core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());
     core.advance_pc();