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Remove consts.rs and just use plain types

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This commit is contained in:
taitep
2025-12-28 12:01:39 +01:00
parent 8024af6b13
commit 9a9bef7dd7
13 changed files with 117 additions and 148 deletions
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5
src/basic_uart.rs
View File

@@ -13,7 +13,6 @@ use std::time::Duration;
use nix::fcntl::fcntl; use nix::fcntl::fcntl;
use nix::fcntl::{FcntlArg, OFlag}; use nix::fcntl::{FcntlArg, OFlag};
use trve::consts::{Addr, Byte};
use trve::exceptions::{MemoryException, MemoryExceptionType}; use trve::exceptions::{MemoryException, MemoryExceptionType};
use trve::mem::MemDeviceInterface; use trve::mem::MemDeviceInterface;
@@ -78,7 +77,7 @@ impl BasicUart {
} }
impl MemDeviceInterface for BasicUart { impl MemDeviceInterface for BasicUart {
fn write_byte(&self, addr: Addr, value: Byte) -> Result<(), MemoryException> { fn write_byte(&self, addr: u64, value: u8) -> Result<(), MemoryException> {
match addr { match addr {
0 => { 0 => {
self.write(value); self.write(value);
@@ -90,7 +89,7 @@ impl MemDeviceInterface for BasicUart {
}), }),
} }
} }
fn read_byte(&self, addr: Addr) -> Result<Byte, MemoryException> { fn read_byte(&self, addr: u64) -> Result<u8, MemoryException> {
match addr { match addr {
0 => Ok(self.read()), 0 => Ok(self.read()),
1 => Ok(1 | (self.can_read() as u8) << 1), 1 => Ok(1 | (self.can_read() as u8) << 1),

9
src/consts.rs
View File

@@ -1,9 +0,0 @@
pub type Byte = u8;
pub type HWord = u16;
pub type Word = u32;
pub type DWord = u64;
pub type RegValue = DWord;
pub type Addr = DWord;
pub type RegId = u8;

13
src/core.rs
View File

@@ -7,7 +7,6 @@
use std::{collections::HashSet, sync::mpsc}; use std::{collections::HashSet, sync::mpsc};
use crate::{ use crate::{
consts::{Addr, RegId, RegValue},
core::commands::CoreCmd, core::commands::CoreCmd,
decode::Instruction, decode::Instruction,
exceptions::{Exception, ExceptionType, MemoryException}, exceptions::{Exception, ExceptionType, MemoryException},
@@ -17,8 +16,8 @@ use crate::{
}; };
pub struct Core { pub struct Core {
pub(crate) x_regs: [RegValue; 32], pub(crate) x_regs: [u64; 32],
pub(crate) pc: Addr, pub(crate) pc: u64,
pub(crate) mem: MemConfig, pub(crate) mem: MemConfig,
command_stream: mpsc::Receiver<CoreCmd>, command_stream: mpsc::Receiver<CoreCmd>,
} }
@@ -119,7 +118,7 @@ impl Core {
fn continue_loop( fn continue_loop(
&mut self, &mut self,
breakpoints: &HashSet<Addr>, breakpoints: &HashSet<u64>,
stopper: oneshot::Receiver<()>, stopper: oneshot::Receiver<()>,
) -> StopReason { ) -> StopReason {
loop { loop {
@@ -177,15 +176,15 @@ impl Core {
dbg!(self.pc, self.x_regs); dbg!(self.pc, self.x_regs);
} }
pub fn reset(&mut self, pc: Addr) { pub fn reset(&mut self, pc: u64) {
self.pc = pc; self.pc = pc;
} }
pub(crate) fn reg_read(&self, id: RegId) -> RegValue { pub(crate) fn reg_read(&self, id: u8) -> u64 {
self.x_regs[id as usize] self.x_regs[id as usize]
} }
pub(crate) fn reg_write(&mut self, id: RegId, value: RegValue) { pub(crate) fn reg_write(&mut self, id: u8, value: u64) {
if id == 0 { if id == 0 {
return; return;
} }

52
src/decode.rs
View File

@@ -4,12 +4,10 @@
// This file is part of TRVE (https://gitea.taitep.se/taitep/trve) // This file is part of TRVE (https://gitea.taitep.se/taitep/trve)
// See LICENSE file in the project root for full license text. // See LICENSE file in the project root for full license text.
use crate::consts::{DWord, RegId, Word}; const MASK_REGISTER: u32 = 0x1f;
const MASK_REGISTER: Word = 0x1f;
#[derive(Debug, Clone, Copy)] #[derive(Debug, Clone, Copy)]
pub struct Instruction(pub Word); pub struct Instruction(pub u32);
#[allow(dead_code)] #[allow(dead_code)]
impl Instruction { impl Instruction {
@@ -26,8 +24,8 @@ impl Instruction {
} }
#[inline] #[inline]
pub fn rd(self) -> RegId { pub fn rd(self) -> u8 {
(self.0 >> 7 & MASK_REGISTER) as RegId (self.0 >> 7 & MASK_REGISTER) as u8
} }
#[inline] #[inline]
@@ -36,13 +34,13 @@ impl Instruction {
} }
#[inline] #[inline]
pub fn rs1(self) -> RegId { pub fn rs1(self) -> u8 {
(self.0 >> 15 & MASK_REGISTER) as RegId (self.0 >> 15 & MASK_REGISTER) as u8
} }
#[inline] #[inline]
pub fn rs2(self) -> RegId { pub fn rs2(self) -> u8 {
(self.0 >> 20 & MASK_REGISTER) as RegId (self.0 >> 20 & MASK_REGISTER) as u8
} }
#[inline] #[inline]
@@ -51,38 +49,38 @@ impl Instruction {
} }
#[inline] #[inline]
pub fn imm_i(self) -> DWord { pub fn imm_i(self) -> u64 {
(self.0 as i32 as i64 >> 20) as DWord (self.0 as i32 as i64 >> 20) as u64
} }
#[inline] #[inline]
pub fn imm_s(self) -> DWord { pub fn imm_s(self) -> u64 {
let imm_11_5 = (self.0 as i32 as i64 >> 25 << 5) as DWord; let imm_11_5 = (self.0 as i32 as i64 >> 25 << 5) as u64;
let imm_4_0 = (self.0 >> 7 & 0x1f) as DWord; let imm_4_0 = (self.0 >> 7 & 0x1f) as u64;
imm_11_5 | imm_4_0 imm_11_5 | imm_4_0
} }
#[inline] #[inline]
pub fn imm_b(self) -> DWord { pub fn imm_b(self) -> u64 {
let imm_12 = ((self.0 & 0x8000_0000) as i32 as i64 >> (31 - 12)) as DWord; let imm_12 = ((self.0 & 0x8000_0000) as i32 as i64 >> (31 - 12)) as u64;
let imm_10_5 = ((self.0 >> 25 & 0x3f) << 5) as DWord; let imm_10_5 = ((self.0 >> 25 & 0x3f) << 5) as u64;
let imm_4_1 = ((self.0 >> 8 & 0xf) << 1) as DWord; let imm_4_1 = ((self.0 >> 8 & 0xf) << 1) as u64;
let imm_11 = ((self.0 >> 7 & 1) << 11) as DWord; let imm_11 = ((self.0 >> 7 & 1) << 11) as u64;
imm_12 | imm_10_5 | imm_4_1 | imm_11 imm_12 | imm_10_5 | imm_4_1 | imm_11
} }
#[inline] #[inline]
pub fn imm_u(self) -> DWord { pub fn imm_u(self) -> u64 {
(self.0 & 0xffff_f000) as i32 as i64 as DWord (self.0 & 0xffff_f000) as i32 as i64 as u64
} }
#[inline] #[inline]
pub fn imm_j(self) -> DWord { pub fn imm_j(self) -> u64 {
let imm_20 = ((self.0 & 0x8000_0000) as i32 as i64 >> (31 - 20)) as DWord; let imm_20 = ((self.0 & 0x8000_0000) as i32 as i64 >> (31 - 20)) as u64;
let imm_10_1 = ((self.0 >> 21 & 0x3ff) << 1) as DWord; let imm_10_1 = ((self.0 >> 21 & 0x3ff) << 1) as u64;
let imm_11 = ((self.0 >> 20 & 1) << 11) as DWord; let imm_11 = ((self.0 >> 20 & 1) << 11) as u64;
let imm_19_12 = ((self.0 >> 12 & 0xff) << 12) as DWord; let imm_19_12 = ((self.0 >> 12 & 0xff) << 12) as u64;
imm_20 | imm_10_1 | imm_11 | imm_19_12 imm_20 | imm_10_1 | imm_11 | imm_19_12
} }

6
src/exceptions.rs
View File

@@ -6,8 +6,6 @@
use int_enum::IntEnum; use int_enum::IntEnum;
use crate::consts::{Addr, DWord};
#[repr(u8)] #[repr(u8)]
#[allow(dead_code)] #[allow(dead_code)]
#[derive(Debug, Clone, Copy, PartialEq, Eq, IntEnum)] #[derive(Debug, Clone, Copy, PartialEq, Eq, IntEnum)]
@@ -43,7 +41,7 @@ impl ExceptionType {
#[derive(Debug, Clone, Copy)] #[derive(Debug, Clone, Copy)]
pub struct Exception { pub struct Exception {
pub type_: ExceptionType, pub type_: ExceptionType,
pub value: DWord, pub value: u64,
} }
#[derive(Debug, Clone, Copy, PartialEq, Eq)] #[derive(Debug, Clone, Copy, PartialEq, Eq)]
@@ -56,7 +54,7 @@ pub enum MemoryExceptionType {
#[derive(Debug, Clone, Copy)] #[derive(Debug, Clone, Copy)]
pub struct MemoryException { pub struct MemoryException {
pub type_: MemoryExceptionType, pub type_: MemoryExceptionType,
pub addr: Addr, pub addr: u64,
} }
impl MemoryException { impl MemoryException {

4
src/execload.rs
View File

@@ -14,9 +14,9 @@ use goblin::{
program_header::PT_LOAD, program_header::PT_LOAD,
}, },
}; };
use trve::{consts::Addr, mem::RAM_START}; use trve::mem::RAM_START;
pub fn load<P: AsRef<Path>>(path: P, ram: &mut [u8]) -> Result<Addr> { pub fn load<P: AsRef<Path>>(path: P, ram: &mut [u8]) -> Result<u64> {
let buf = fs::read(path)?; let buf = fs::read(path)?;
match Object::parse(&buf)? { match Object::parse(&buf)? {

11
src/gdb.rs
View File

@@ -11,7 +11,6 @@ use std::{
}; };
use crate::{ use crate::{
consts::{Addr, RegValue},
core::commands::CoreCmd, core::commands::CoreCmd,
exceptions::{ExceptionType, MemoryExceptionType}, exceptions::{ExceptionType, MemoryExceptionType},
}; };
@@ -19,14 +18,14 @@ use crate::{
pub(crate) enum DebugCommand { pub(crate) enum DebugCommand {
GetRegs(oneshot::Sender<RegsResponse>), GetRegs(oneshot::Sender<RegsResponse>),
ReadMem { ReadMem {
addr: Addr, addr: u64,
len: u64, len: u64,
responder: oneshot::Sender<Result<Vec<u8>, MemoryExceptionType>>, responder: oneshot::Sender<Result<Vec<u8>, MemoryExceptionType>>,
}, },
Step(oneshot::Sender<StopReason>), Step(oneshot::Sender<StopReason>),
Continue(oneshot::Sender<StopReason>, oneshot::Receiver<()>), Continue(oneshot::Sender<StopReason>, oneshot::Receiver<()>),
SetBreakpoint(Addr), SetBreakpoint(u64),
RemoveBreakpoint(Addr), RemoveBreakpoint(u64),
ExitDebugMode, ExitDebugMode,
} }
@@ -65,8 +64,8 @@ impl StopReason {
} }
pub(crate) struct RegsResponse { pub(crate) struct RegsResponse {
pub x_regs: [RegValue; 32], pub x_regs: [u64; 32],
pub pc: Addr, pub pc: u64,
} }
pub fn run_stub(cmd_sender: mpsc::Sender<CoreCmd>) { pub fn run_stub(cmd_sender: mpsc::Sender<CoreCmd>) {

3
src/instructions.rs
View File

@@ -10,7 +10,6 @@ mod macros;
mod rvi; mod rvi;
use crate::{ use crate::{
consts::DWord,
core::Core, core::Core,
decode::Instruction, decode::Instruction,
exceptions::{ exceptions::{
@@ -22,7 +21,7 @@ use crate::{
fn illegal(instr: Instruction) -> Result<(), Exception> { fn illegal(instr: Instruction) -> Result<(), Exception> {
Err(Exception { Err(Exception {
type_: IllegalInstruction, type_: IllegalInstruction,
value: instr.0 as DWord, value: instr.0 as u64,
}) })
} }

34
src/instructions/rvi.rs
View File

@@ -4,7 +4,7 @@
// This file is part of TRVE (https://gitea.taitep.se/taitep/trve) // This file is part of TRVE (https://gitea.taitep.se/taitep/trve)
// See LICENSE file in the project root for full license text. // See LICENSE file in the project root for full license text.
use crate::{consts::RegValue, core::Core, decode::Instruction, exceptions::Exception}; use crate::{core::Core, decode::Instruction, exceptions::Exception};
use std::ops::{BitAnd, BitOr, BitXor}; use std::ops::{BitAnd, BitOr, BitXor};
@@ -12,42 +12,38 @@ mod mem;
pub use mem::*; pub use mem::*;
instr_op!(add, addi, RegValue::wrapping_add); instr_op!(add, addi, u64::wrapping_add);
instr_op!( instr_op!(addw, addiw, |a, b| u64::wrapping_add(a, b) as i32 as i64
addw, as u64);
addiw, instr_op_r!(sub, u64::wrapping_sub);
|a, b| RegValue::wrapping_add(a, b) as i32 as i64 as RegValue instr_op_r!(subw, |a, b| u64::wrapping_sub(a, b) as i32 as i64 as u64);
);
instr_op_r!(sub, RegValue::wrapping_sub);
instr_op_r!(subw, |a, b| RegValue::wrapping_sub(a, b) as i32 as i64
as RegValue);
instr_op!(and, andi, RegValue::bitand); instr_op!(and, andi, u64::bitand);
instr_op!(or, ori, RegValue::bitor); instr_op!(or, ori, u64::bitor);
instr_op!(xor, xori, RegValue::bitxor); instr_op!(xor, xori, u64::bitxor);
instr_op!(sll, slli, |x, shamt| x << (shamt & 0b111111)); instr_op!(sll, slli, |x, shamt| x << (shamt & 0b111111));
instr_op!( instr_op!(
sllw, sllw,
slliw, slliw,
|x, shamt| (x << (shamt & 0b11111)) as i32 as i64 as RegValue |x, shamt| (x << (shamt & 0b11111)) as i32 as i64 as u64
); );
instr_op!(srl, srli, |x, shamt| x >> (shamt & 0b111111)); instr_op!(srl, srli, |x, shamt| x >> (shamt & 0b111111));
instr_op!( instr_op!(
srlw, srlw,
srliw, srliw,
|x, shamt| (x >> (shamt & 0b11111)) as i32 as i64 as RegValue |x, shamt| (x >> (shamt & 0b11111)) as i32 as i64 as u64
); );
instr_op!(sra, srai, |x, shamt| (x as i64 >> (shamt & 0b111111)) instr_op!(sra, srai, |x, shamt| (x as i64 >> (shamt & 0b111111))
as RegValue); as u64);
instr_op!( instr_op!(
sraw, sraw,
sraiw, sraiw,
|x, shamt| (x as i32 >> (shamt & 0b11111)) as i64 as RegValue |x, shamt| (x as i32 >> (shamt & 0b11111)) as i64 as u64
); );
instr_op!(sltu, sltiu, |a, b| (a < b) as RegValue); instr_op!(sltu, sltiu, |a, b| (a < b) as u64);
instr_op!(slt, slti, |a, b| ((a as i64) < (b as i64)) as RegValue); instr_op!(slt, slti, |a, b| ((a as i64) < (b as i64)) as u64);
pub fn lui(core: &mut Core, instr: Instruction) -> Result<(), Exception> { pub fn lui(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
core.reg_write(instr.rd(), instr.imm_u()); core.reg_write(instr.rd(), instr.imm_u());

25
src/instructions/rvi/mem.rs
View File

@@ -4,12 +4,7 @@
// This file is part of TRVE (https://gitea.taitep.se/taitep/trve) // This file is part of TRVE (https://gitea.taitep.se/taitep/trve)
// See LICENSE file in the project root for full license text. // See LICENSE file in the project root for full license text.
use crate::{ use crate::{core::Core, exceptions::Exception, instructions::Instruction};
consts::{Byte, DWord, HWord, Word},
core::Core,
exceptions::Exception,
instructions::Instruction,
};
pub fn sd(core: &mut Core, instr: Instruction) -> Result<(), Exception> { pub fn sd(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
@@ -35,7 +30,7 @@ pub fn ld(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
pub fn sw(core: &mut Core, instr: Instruction) -> Result<(), Exception> { pub fn sw(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
let value = core.reg_read(instr.rs2()) as Word; let value = core.reg_read(instr.rs2()) as u32;
core.mem core.mem
.write_word(addr, value) .write_word(addr, value)
.map_err(|e| e.to_exception_store())?; .map_err(|e| e.to_exception_store())?;
@@ -49,7 +44,7 @@ pub fn lw(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
instr.rd(), instr.rd(),
core.mem core.mem
.read_word(addr) .read_word(addr)
.map_err(|e| e.to_exception_load())? as i32 as i64 as DWord, .map_err(|e| e.to_exception_load())? as i32 as i64 as u64,
); );
core.advance_pc(); core.advance_pc();
Ok(()) Ok(())
@@ -61,7 +56,7 @@ pub fn lwu(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
instr.rd(), instr.rd(),
core.mem core.mem
.read_word(addr) .read_word(addr)
.map_err(|e| e.to_exception_load())? as DWord, .map_err(|e| e.to_exception_load())? as u64,
); );
core.advance_pc(); core.advance_pc();
Ok(()) Ok(())
@@ -69,7 +64,7 @@ pub fn lwu(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
pub fn sh(core: &mut Core, instr: Instruction) -> Result<(), Exception> { pub fn sh(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
let value = core.reg_read(instr.rs2()) as HWord; let value = core.reg_read(instr.rs2()) as u16;
core.mem core.mem
.write_hword(addr, value) .write_hword(addr, value)
.map_err(|e| e.to_exception_store())?; .map_err(|e| e.to_exception_store())?;
@@ -83,7 +78,7 @@ pub fn lh(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
instr.rd(), instr.rd(),
core.mem core.mem
.read_hword(addr) .read_hword(addr)
.map_err(|e| e.to_exception_load())? as i16 as i64 as DWord, .map_err(|e| e.to_exception_load())? as i16 as i64 as u64,
); );
core.advance_pc(); core.advance_pc();
Ok(()) Ok(())
@@ -95,7 +90,7 @@ pub fn lhu(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
instr.rd(), instr.rd(),
core.mem core.mem
.read_hword(addr) .read_hword(addr)
.map_err(|e| e.to_exception_load())? as DWord, .map_err(|e| e.to_exception_load())? as u64,
); );
core.advance_pc(); core.advance_pc();
Ok(()) Ok(())
@@ -103,7 +98,7 @@ pub fn lhu(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
pub fn sb(core: &mut Core, instr: Instruction) -> Result<(), Exception> { pub fn sb(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
let value = core.reg_read(instr.rs2()) as Byte; let value = core.reg_read(instr.rs2()) as u8;
core.mem core.mem
.write_byte(addr, value) .write_byte(addr, value)
.map_err(|e| e.to_exception_store())?; .map_err(|e| e.to_exception_store())?;
@@ -117,7 +112,7 @@ pub fn lb(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
instr.rd(), instr.rd(),
core.mem core.mem
.read_byte(addr) .read_byte(addr)
.map_err(|e| e.to_exception_load())? as i8 as i64 as DWord, .map_err(|e| e.to_exception_load())? as i8 as i64 as u64,
); );
core.advance_pc(); core.advance_pc();
Ok(()) Ok(())
@@ -129,7 +124,7 @@ pub fn lbu(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
instr.rd(), instr.rd(),
core.mem core.mem
.read_byte(addr) .read_byte(addr)
.map_err(|e| e.to_exception_load())? as DWord, .map_err(|e| e.to_exception_load())? as u64,
); );
core.advance_pc(); core.advance_pc();
Ok(()) Ok(())

1
src/lib.rs
View File

@@ -1,4 +1,3 @@
pub mod consts;
pub mod core; pub mod core;
mod decode; mod decode;
pub mod exceptions; pub mod exceptions;

9
src/main.rs
View File

@@ -9,7 +9,6 @@ use std::{path::PathBuf, sync::Arc, time::Duration};
use clap::Parser; use clap::Parser;
use trve::{ use trve::{
consts::{Addr, Byte, DWord, HWord, Word},
core::Core, core::Core,
exceptions::MemoryException, exceptions::MemoryException,
gdb, gdb,
@@ -70,22 +69,22 @@ mod basic_uart;
struct DbgOut; struct DbgOut;
impl MemDeviceInterface for DbgOut { impl MemDeviceInterface for DbgOut {
fn write_dword(&self, addr: Addr, value: DWord) -> Result<(), MemoryException> { fn write_dword(&self, addr: u64, value: u64) -> Result<(), MemoryException> {
eprintln!("Wrote DWord {value:016x} to Debug-Out address {addr:x}"); eprintln!("Wrote DWord {value:016x} to Debug-Out address {addr:x}");
Ok(()) Ok(())
} }
fn write_word(&self, addr: Addr, value: Word) -> Result<(), MemoryException> { fn write_word(&self, addr: u64, value: u32) -> Result<(), MemoryException> {
eprintln!("Wrote Word {value:08x} to Debug-Out address {addr:x}"); eprintln!("Wrote Word {value:08x} to Debug-Out address {addr:x}");
Ok(()) Ok(())
} }
fn write_hword(&self, addr: Addr, value: HWord) -> Result<(), MemoryException> { fn write_hword(&self, addr: u64, value: u16) -> Result<(), MemoryException> {
eprintln!("Wrote HWord {value:04x} to Debug-Out address {addr:x}"); eprintln!("Wrote HWord {value:04x} to Debug-Out address {addr:x}");
Ok(()) Ok(())
} }
fn write_byte(&self, addr: Addr, value: Byte) -> Result<(), MemoryException> { fn write_byte(&self, addr: u64, value: u8) -> Result<(), MemoryException> {
eprintln!("Wrote Byte {value:02x} to Debug-Out address {addr:x}"); eprintln!("Wrote Byte {value:02x} to Debug-Out address {addr:x}");
Ok(()) Ok(())
} }

93
src/mem.rs
View File

@@ -11,14 +11,11 @@ use std::sync::{
use memmap2::MmapMut; use memmap2::MmapMut;
use crate::{ use crate::exceptions::{MemoryException, MemoryExceptionType};
consts::{Addr, Byte, DWord, HWord, Word},
exceptions::{MemoryException, MemoryExceptionType},
};
pub type PageNum = usize; pub type PageNum = usize;
pub const RAM_START: Addr = 0x8000_0000; pub const RAM_START: u64 = 0x8000_0000;
#[derive(Clone)] #[derive(Clone)]
pub struct MemConfig { pub struct MemConfig {
@@ -27,7 +24,7 @@ pub struct MemConfig {
} }
impl MemConfig { impl MemConfig {
pub fn memory_mapping_type(&self, addr: Addr) -> Option<MemoryMappingType> { pub fn memory_mapping_type(&self, addr: u64) -> Option<MemoryMappingType> {
if addr >= RAM_START { if addr >= RAM_START {
Some(MemoryMappingType::RAM) Some(MemoryMappingType::RAM)
} else { } else {
@@ -37,7 +34,7 @@ impl MemConfig {
} }
} }
pub fn read_dword(&self, addr: Addr) -> Result<DWord, MemoryException> { pub fn read_dword(&self, addr: u64) -> Result<u64, MemoryException> {
if addr >= RAM_START { if addr >= RAM_START {
self.ram.read_dword(addr - RAM_START) self.ram.read_dword(addr - RAM_START)
} else { } else {
@@ -55,7 +52,7 @@ impl MemConfig {
interface.read_dword(addr) interface.read_dword(addr)
} }
} }
pub fn read_word(&self, addr: Addr) -> Result<Word, MemoryException> { pub fn read_word(&self, addr: u64) -> Result<u32, MemoryException> {
if addr >= RAM_START { if addr >= RAM_START {
self.ram.read_word(addr - RAM_START) self.ram.read_word(addr - RAM_START)
} else { } else {
@@ -73,7 +70,7 @@ impl MemConfig {
interface.read_word(addr) interface.read_word(addr)
} }
} }
pub fn read_hword(&self, addr: Addr) -> Result<HWord, MemoryException> { pub fn read_hword(&self, addr: u64) -> Result<u16, MemoryException> {
if addr >= RAM_START { if addr >= RAM_START {
self.ram.read_hword(addr - RAM_START) self.ram.read_hword(addr - RAM_START)
} else { } else {
@@ -90,7 +87,7 @@ impl MemConfig {
interface.read_hword(addr) interface.read_hword(addr)
} }
} }
pub fn read_byte(&self, addr: Addr) -> Result<Byte, MemoryException> { pub fn read_byte(&self, addr: u64) -> Result<u8, MemoryException> {
if addr >= RAM_START { if addr >= RAM_START {
self.ram.read_byte(addr - RAM_START) self.ram.read_byte(addr - RAM_START)
} else { } else {
@@ -102,7 +99,7 @@ impl MemConfig {
} }
} }
pub fn write_dword(&self, addr: Addr, value: DWord) -> Result<(), MemoryException> { pub fn write_dword(&self, addr: u64, value: u64) -> Result<(), MemoryException> {
if addr >= RAM_START { if addr >= RAM_START {
self.ram.write_dword(addr - RAM_START, value) self.ram.write_dword(addr - RAM_START, value)
} else { } else {
@@ -119,7 +116,7 @@ impl MemConfig {
interface.write_dword(addr, value) interface.write_dword(addr, value)
} }
} }
pub fn write_word(&self, addr: Addr, value: Word) -> Result<(), MemoryException> { pub fn write_word(&self, addr: u64, value: u32) -> Result<(), MemoryException> {
if addr >= RAM_START { if addr >= RAM_START {
self.ram.write_word(addr - RAM_START, value) self.ram.write_word(addr - RAM_START, value)
} else { } else {
@@ -136,7 +133,7 @@ impl MemConfig {
interface.write_word(addr, value) interface.write_word(addr, value)
} }
} }
pub fn write_hword(&self, addr: Addr, value: HWord) -> Result<(), MemoryException> { pub fn write_hword(&self, addr: u64, value: u16) -> Result<(), MemoryException> {
if addr >= RAM_START { if addr >= RAM_START {
self.ram.write_hword(addr - RAM_START, value) self.ram.write_hword(addr - RAM_START, value)
} else { } else {
@@ -153,7 +150,7 @@ impl MemConfig {
interface.write_hword(addr, value) interface.write_hword(addr, value)
} }
} }
pub fn write_byte(&self, addr: Addr, value: Byte) -> Result<(), MemoryException> { pub fn write_byte(&self, addr: u64, value: u8) -> Result<(), MemoryException> {
if addr >= RAM_START { if addr >= RAM_START {
self.ram.write_byte(addr - RAM_START, value) self.ram.write_byte(addr - RAM_START, value)
} else { } else {
@@ -165,7 +162,7 @@ impl MemConfig {
} }
} }
pub fn get_atomic_dword(&self, addr: Addr) -> Result<&AtomicU64, MemoryException> { pub fn get_atomic_dword(&self, addr: u64) -> Result<&AtomicU64, MemoryException> {
if !addr.is_multiple_of(8) { if !addr.is_multiple_of(8) {
return Err(MemoryException { return Err(MemoryException {
type_: MemoryExceptionType::AddressMisaligned, type_: MemoryExceptionType::AddressMisaligned,
@@ -184,7 +181,7 @@ impl MemConfig {
}) })
} }
} }
pub fn get_atomic_word(&self, addr: Addr) -> Result<&AtomicU32, MemoryException> { pub fn get_atomic_word(&self, addr: u64) -> Result<&AtomicU32, MemoryException> {
if !addr.is_multiple_of(4) { if !addr.is_multiple_of(4) {
return Err(MemoryException { return Err(MemoryException {
type_: MemoryExceptionType::AddressMisaligned, type_: MemoryExceptionType::AddressMisaligned,
@@ -262,14 +259,14 @@ impl Ram {
} }
#[inline] #[inline]
pub fn read_dword(&self, addr: Addr) -> Result<DWord, MemoryException> { pub fn read_dword(&self, addr: u64) -> Result<u64, MemoryException> {
if !addr.is_multiple_of(8) { if !addr.is_multiple_of(8) {
let high_word_addr = addr.wrapping_add(4); let high_word_addr = addr.wrapping_add(4);
let low_word = self.read_byte(addr)?; let low_word = self.read_byte(addr)?;
let high_word = self.read_byte(high_word_addr)?; let high_word = self.read_byte(high_word_addr)?;
return Ok((low_word as DWord) | (high_word as DWord) << 32); return Ok((low_word as u64) | (high_word as u64) << 32);
} }
let index = (addr / 8) as usize; let index = (addr / 8) as usize;
@@ -284,14 +281,14 @@ impl Ram {
.load(Relaxed)) .load(Relaxed))
} }
#[inline] #[inline]
pub fn read_word(&self, addr: Addr) -> Result<Word, MemoryException> { pub fn read_word(&self, addr: u64) -> Result<u32, MemoryException> {
if !addr.is_multiple_of(4) { if !addr.is_multiple_of(4) {
let high_hword_addr = addr.wrapping_add(2); let high_hword_addr = addr.wrapping_add(2);
let low_hword = self.read_hword(addr)?; let low_hword = self.read_hword(addr)?;
let high_hword = self.read_hword(high_hword_addr)?; let high_hword = self.read_hword(high_hword_addr)?;
return Ok((low_hword as Word) | (high_hword as Word) << 16); return Ok((low_hword as u32) | (high_hword as u32) << 16);
} }
let index = (addr / 4) as usize; let index = (addr / 4) as usize;
@@ -306,14 +303,14 @@ impl Ram {
.load(Relaxed)) .load(Relaxed))
} }
#[inline] #[inline]
pub fn read_hword(&self, addr: Addr) -> Result<HWord, MemoryException> { pub fn read_hword(&self, addr: u64) -> Result<u16, MemoryException> {
if !addr.is_multiple_of(2) { if !addr.is_multiple_of(2) {
let high_byte_addr = addr.wrapping_add(1); let high_byte_addr = addr.wrapping_add(1);
let low_byte = self.read_byte(addr)?; let low_byte = self.read_byte(addr)?;
let high_byte = self.read_byte(high_byte_addr)?; let high_byte = self.read_byte(high_byte_addr)?;
return Ok((low_byte as HWord) | (high_byte as HWord) << 8); return Ok((low_byte as u16) | (high_byte as u16) << 8);
} }
let index = (addr / 2) as usize; let index = (addr / 2) as usize;
@@ -328,7 +325,7 @@ impl Ram {
.load(Relaxed)) .load(Relaxed))
} }
#[inline] #[inline]
pub fn read_byte(&self, addr: Addr) -> Result<Byte, MemoryException> { pub fn read_byte(&self, addr: u64) -> Result<u8, MemoryException> {
Ok(self Ok(self
.buf_atomic() .buf_atomic()
.get(addr as usize) .get(addr as usize)
@@ -340,10 +337,10 @@ impl Ram {
} }
#[inline] #[inline]
pub fn write_dword(&self, addr: Addr, value: DWord) -> Result<(), MemoryException> { pub fn write_dword(&self, addr: u64, value: u64) -> Result<(), MemoryException> {
if !addr.is_multiple_of(8) { if !addr.is_multiple_of(8) {
let low_word = value as Word; let low_word = value as u32;
let high_word = (value >> 32) as Word; let high_word = (value >> 32) as u32;
let high_word_address = addr.wrapping_add(4); let high_word_address = addr.wrapping_add(4);
@@ -365,10 +362,10 @@ impl Ram {
Ok(()) Ok(())
} }
#[inline] #[inline]
pub fn write_word(&self, addr: Addr, value: Word) -> Result<(), MemoryException> { pub fn write_word(&self, addr: u64, value: u32) -> Result<(), MemoryException> {
if !addr.is_multiple_of(4) { if !addr.is_multiple_of(4) {
let low_hword = value as HWord; let low_hword = value as u16;
let high_hword = (value >> 16) as HWord; let high_hword = (value >> 16) as u16;
let high_hword_address = addr.wrapping_add(2); let high_hword_address = addr.wrapping_add(2);
@@ -390,10 +387,10 @@ impl Ram {
Ok(()) Ok(())
} }
#[inline] #[inline]
pub fn write_hword(&self, addr: Addr, value: HWord) -> Result<(), MemoryException> { pub fn write_hword(&self, addr: u64, value: u16) -> Result<(), MemoryException> {
if !addr.is_multiple_of(2) { if !addr.is_multiple_of(2) {
let low_byte = value as Byte; let low_byte = value as u8;
let high_byte = (value >> 8) as Byte; let high_byte = (value >> 8) as u8;
let high_byte_address = addr.wrapping_add(1); let high_byte_address = addr.wrapping_add(1);
@@ -415,7 +412,7 @@ impl Ram {
Ok(()) Ok(())
} }
#[inline] #[inline]
pub fn write_byte(&self, addr: Addr, value: Byte) -> Result<(), MemoryException> { pub fn write_byte(&self, addr: u64, value: u8) -> Result<(), MemoryException> {
self.buf_atomic() self.buf_atomic()
.get(addr as usize) .get(addr as usize)
.ok_or(MemoryException { .ok_or(MemoryException {
@@ -437,7 +434,7 @@ const MMIO_SECOND_LEVEL_ENTRIES: usize = MMIO_ROOT_PAGE_SIZE / MMIO_SECOND_LEVEL
pub struct MmioRoot(Box<[Option<MmioSecondLevel>; MMIO_ROOT_ENTRIES]>); pub struct MmioRoot(Box<[Option<MmioSecondLevel>; MMIO_ROOT_ENTRIES]>);
impl MmioRoot { impl MmioRoot {
pub fn insert(&mut self, base_addr: Addr, interface: Arc<dyn MemDeviceInterface>) { pub fn insert(&mut self, base_addr: u64, interface: Arc<dyn MemDeviceInterface>) {
assert!(base_addr.is_multiple_of(MMIO_SECOND_LEVEL_PAGE_SIZE as u64)); assert!(base_addr.is_multiple_of(MMIO_SECOND_LEVEL_PAGE_SIZE as u64));
assert!(base_addr < RAM_START); assert!(base_addr < RAM_START);
@@ -452,7 +449,7 @@ impl MmioRoot {
} }
} }
pub fn insert_full(&mut self, base_addr: Addr, interface: Arc<dyn MemDeviceInterface>) { pub fn insert_full(&mut self, base_addr: u64, interface: Arc<dyn MemDeviceInterface>) {
assert!(base_addr.is_multiple_of(MMIO_ROOT_PAGE_SIZE as u64)); assert!(base_addr.is_multiple_of(MMIO_ROOT_PAGE_SIZE as u64));
assert!(base_addr < RAM_START); assert!(base_addr < RAM_START);
@@ -461,7 +458,7 @@ impl MmioRoot {
self.0[page_id] = Some(MmioSecondLevel::Interface(interface)); self.0[page_id] = Some(MmioSecondLevel::Interface(interface));
} }
fn get_device(&self, addr: Addr) -> Option<(Arc<dyn MemDeviceInterface>, Addr)> { fn get_device(&self, addr: u64) -> Option<(Arc<dyn MemDeviceInterface>, u64)> {
debug_assert!(addr < RAM_START); debug_assert!(addr < RAM_START);
let page_id = addr as usize / MMIO_SECOND_LEVEL_PAGE_SIZE; let page_id = addr as usize / MMIO_SECOND_LEVEL_PAGE_SIZE;
@@ -469,10 +466,10 @@ impl MmioRoot {
self.0[root_page_id] self.0[root_page_id]
.as_ref() .as_ref()
.and_then(|s| s.get_device(addr % MMIO_ROOT_PAGE_SIZE as Addr)) .and_then(|s| s.get_device(addr % MMIO_ROOT_PAGE_SIZE as u64))
} }
fn crosses_boundary(&self, addr: Addr, size: Addr) -> bool { fn crosses_boundary(&self, addr: u64, size: u64) -> bool {
if addr >= RAM_START { if addr >= RAM_START {
return false; return false;
} }
@@ -514,12 +511,12 @@ enum MmioSecondLevel {
} }
impl MmioSecondLevel { impl MmioSecondLevel {
fn get_device(&self, addr: Addr) -> Option<(Arc<dyn MemDeviceInterface>, Addr)> { fn get_device(&self, addr: u64) -> Option<(Arc<dyn MemDeviceInterface>, u64)> {
let page_id = addr as usize / MMIO_SECOND_LEVEL_PAGE_SIZE; let page_id = addr as usize / MMIO_SECOND_LEVEL_PAGE_SIZE;
match self { match self {
Self::SubTable(t) => t[page_id] Self::SubTable(t) => t[page_id]
.as_ref() .as_ref()
.map(|i| (i.clone(), addr % MMIO_SECOND_LEVEL_PAGE_SIZE as Addr)), .map(|i| (i.clone(), addr % MMIO_SECOND_LEVEL_PAGE_SIZE as u64)),
Self::Interface(i) => Some((i.clone(), addr)), Self::Interface(i) => Some((i.clone(), addr)),
} }
@@ -534,50 +531,50 @@ impl Default for MmioSecondLevel {
#[allow(unused_variables)] #[allow(unused_variables)]
pub trait MemDeviceInterface { pub trait MemDeviceInterface {
fn write_dword(&self, addr: Addr, value: DWord) -> Result<(), MemoryException> { fn write_dword(&self, addr: u64, value: u64) -> Result<(), MemoryException> {
Err(MemoryException { Err(MemoryException {
type_: MemoryExceptionType::AccessFault, type_: MemoryExceptionType::AccessFault,
addr, addr,
}) })
} }
fn write_word(&self, addr: Addr, value: Word) -> Result<(), MemoryException> { fn write_word(&self, addr: u64, value: u32) -> Result<(), MemoryException> {
Err(MemoryException { Err(MemoryException {
type_: MemoryExceptionType::AccessFault, type_: MemoryExceptionType::AccessFault,
addr, addr,
}) })
} }
fn write_hword(&self, addr: Addr, value: HWord) -> Result<(), MemoryException> { fn write_hword(&self, addr: u64, value: u16) -> Result<(), MemoryException> {
Err(MemoryException { Err(MemoryException {
type_: MemoryExceptionType::AccessFault, type_: MemoryExceptionType::AccessFault,
addr, addr,
}) })
} }
fn write_byte(&self, addr: Addr, value: Byte) -> Result<(), MemoryException> { fn write_byte(&self, addr: u64, value: u8) -> Result<(), MemoryException> {
Err(MemoryException { Err(MemoryException {
type_: MemoryExceptionType::AccessFault, type_: MemoryExceptionType::AccessFault,
addr, addr,
}) })
} }
fn read_dword(&self, addr: Addr) -> Result<DWord, MemoryException> { fn read_dword(&self, addr: u64) -> Result<u64, MemoryException> {
Err(MemoryException { Err(MemoryException {
type_: MemoryExceptionType::AccessFault, type_: MemoryExceptionType::AccessFault,
addr, addr,
}) })
} }
fn read_word(&self, addr: Addr) -> Result<Word, MemoryException> { fn read_word(&self, addr: u64) -> Result<u32, MemoryException> {
Err(MemoryException { Err(MemoryException {
type_: MemoryExceptionType::AccessFault, type_: MemoryExceptionType::AccessFault,
addr, addr,
}) })
} }
fn read_hword(&self, addr: Addr) -> Result<HWord, MemoryException> { fn read_hword(&self, addr: u64) -> Result<u16, MemoryException> {
Err(MemoryException { Err(MemoryException {
type_: MemoryExceptionType::AccessFault, type_: MemoryExceptionType::AccessFault,
addr, addr,
}) })
} }
fn read_byte(&self, addr: Addr) -> Result<Byte, MemoryException> { fn read_byte(&self, addr: u64) -> Result<u8, MemoryException> {
Err(MemoryException { Err(MemoryException {
type_: MemoryExceptionType::AccessFault, type_: MemoryExceptionType::AccessFault,
addr, addr,