From 9a9bef7dd7dce7d5c10b7cf49a42478ad85829ac Mon Sep 17 00:00:00 2001 From: taitep Date: Sun, 28 Dec 2025 12:01:39 +0100 Subject: [PATCH] Remove consts.rs and just use plain types --- src/basic_uart.rs | 5 +- src/consts.rs | 9 ---- src/core.rs | 13 +++--- src/decode.rs | 52 ++++++++++----------- src/exceptions.rs | 6 +-- src/execload.rs | 4 +- src/gdb.rs | 11 ++--- src/instructions.rs | 3 +- src/instructions/rvi.rs | 34 ++++++-------- src/instructions/rvi/mem.rs | 25 ++++------ src/lib.rs | 1 - src/main.rs | 9 ++-- src/mem.rs | 93 ++++++++++++++++++------------------- 13 files changed, 117 insertions(+), 148 deletions(-) delete mode 100644 src/consts.rs diff --git a/src/basic_uart.rs b/src/basic_uart.rs index e5b91f3..8317950 100644 --- a/src/basic_uart.rs +++ b/src/basic_uart.rs @@ -13,7 +13,6 @@ use std::time::Duration; use nix::fcntl::fcntl; use nix::fcntl::{FcntlArg, OFlag}; -use trve::consts::{Addr, Byte}; use trve::exceptions::{MemoryException, MemoryExceptionType}; use trve::mem::MemDeviceInterface; @@ -78,7 +77,7 @@ impl BasicUart { } impl MemDeviceInterface for BasicUart { - fn write_byte(&self, addr: Addr, value: Byte) -> Result<(), MemoryException> { + fn write_byte(&self, addr: u64, value: u8) -> Result<(), MemoryException> { match addr { 0 => { self.write(value); @@ -90,7 +89,7 @@ impl MemDeviceInterface for BasicUart { }), } } - fn read_byte(&self, addr: Addr) -> Result { + fn read_byte(&self, addr: u64) -> Result { match addr { 0 => Ok(self.read()), 1 => Ok(1 | (self.can_read() as u8) << 1), diff --git a/src/consts.rs b/src/consts.rs deleted file mode 100644 index 1e52c92..0000000 --- a/src/consts.rs +++ /dev/null @@ -1,9 +0,0 @@ -pub type Byte = u8; -pub type HWord = u16; -pub type Word = u32; -pub type DWord = u64; - -pub type RegValue = DWord; -pub type Addr = DWord; - -pub type RegId = u8; diff --git a/src/core.rs b/src/core.rs index eb0549f..07df2f5 100644 --- a/src/core.rs +++ b/src/core.rs @@ -7,7 +7,6 @@ use std::{collections::HashSet, sync::mpsc}; use crate::{ - consts::{Addr, RegId, RegValue}, core::commands::CoreCmd, decode::Instruction, exceptions::{Exception, ExceptionType, MemoryException}, @@ -17,8 +16,8 @@ use crate::{ }; pub struct Core { - pub(crate) x_regs: [RegValue; 32], - pub(crate) pc: Addr, + pub(crate) x_regs: [u64; 32], + pub(crate) pc: u64, pub(crate) mem: MemConfig, command_stream: mpsc::Receiver, } @@ -119,7 +118,7 @@ impl Core { fn continue_loop( &mut self, - breakpoints: &HashSet, + breakpoints: &HashSet, stopper: oneshot::Receiver<()>, ) -> StopReason { loop { @@ -177,15 +176,15 @@ impl Core { dbg!(self.pc, self.x_regs); } - pub fn reset(&mut self, pc: Addr) { + pub fn reset(&mut self, pc: u64) { self.pc = pc; } - pub(crate) fn reg_read(&self, id: RegId) -> RegValue { + pub(crate) fn reg_read(&self, id: u8) -> u64 { self.x_regs[id as usize] } - pub(crate) fn reg_write(&mut self, id: RegId, value: RegValue) { + pub(crate) fn reg_write(&mut self, id: u8, value: u64) { if id == 0 { return; } diff --git a/src/decode.rs b/src/decode.rs index e24bac0..616f7f7 100644 --- a/src/decode.rs +++ b/src/decode.rs @@ -4,12 +4,10 @@ // This file is part of TRVE (https://gitea.taitep.se/taitep/trve) // See LICENSE file in the project root for full license text. -use crate::consts::{DWord, RegId, Word}; - -const MASK_REGISTER: Word = 0x1f; +const MASK_REGISTER: u32 = 0x1f; #[derive(Debug, Clone, Copy)] -pub struct Instruction(pub Word); +pub struct Instruction(pub u32); #[allow(dead_code)] impl Instruction { @@ -26,8 +24,8 @@ impl Instruction { } #[inline] - pub fn rd(self) -> RegId { - (self.0 >> 7 & MASK_REGISTER) as RegId + pub fn rd(self) -> u8 { + (self.0 >> 7 & MASK_REGISTER) as u8 } #[inline] @@ -36,13 +34,13 @@ impl Instruction { } #[inline] - pub fn rs1(self) -> RegId { - (self.0 >> 15 & MASK_REGISTER) as RegId + pub fn rs1(self) -> u8 { + (self.0 >> 15 & MASK_REGISTER) as u8 } #[inline] - pub fn rs2(self) -> RegId { - (self.0 >> 20 & MASK_REGISTER) as RegId + pub fn rs2(self) -> u8 { + (self.0 >> 20 & MASK_REGISTER) as u8 } #[inline] @@ -51,38 +49,38 @@ impl Instruction { } #[inline] - pub fn imm_i(self) -> DWord { - (self.0 as i32 as i64 >> 20) as DWord + pub fn imm_i(self) -> u64 { + (self.0 as i32 as i64 >> 20) as u64 } #[inline] - pub fn imm_s(self) -> DWord { - let imm_11_5 = (self.0 as i32 as i64 >> 25 << 5) as DWord; - let imm_4_0 = (self.0 >> 7 & 0x1f) as DWord; + pub fn imm_s(self) -> u64 { + let imm_11_5 = (self.0 as i32 as i64 >> 25 << 5) as u64; + let imm_4_0 = (self.0 >> 7 & 0x1f) as u64; imm_11_5 | imm_4_0 } #[inline] - pub fn imm_b(self) -> DWord { - let imm_12 = ((self.0 & 0x8000_0000) as i32 as i64 >> (31 - 12)) as DWord; - let imm_10_5 = ((self.0 >> 25 & 0x3f) << 5) as DWord; - let imm_4_1 = ((self.0 >> 8 & 0xf) << 1) as DWord; - let imm_11 = ((self.0 >> 7 & 1) << 11) as DWord; + pub fn imm_b(self) -> u64 { + let imm_12 = ((self.0 & 0x8000_0000) as i32 as i64 >> (31 - 12)) as u64; + let imm_10_5 = ((self.0 >> 25 & 0x3f) << 5) as u64; + let imm_4_1 = ((self.0 >> 8 & 0xf) << 1) as u64; + let imm_11 = ((self.0 >> 7 & 1) << 11) as u64; imm_12 | imm_10_5 | imm_4_1 | imm_11 } #[inline] - pub fn imm_u(self) -> DWord { - (self.0 & 0xffff_f000) as i32 as i64 as DWord + pub fn imm_u(self) -> u64 { + (self.0 & 0xffff_f000) as i32 as i64 as u64 } #[inline] - pub fn imm_j(self) -> DWord { - let imm_20 = ((self.0 & 0x8000_0000) as i32 as i64 >> (31 - 20)) as DWord; - let imm_10_1 = ((self.0 >> 21 & 0x3ff) << 1) as DWord; - let imm_11 = ((self.0 >> 20 & 1) << 11) as DWord; - let imm_19_12 = ((self.0 >> 12 & 0xff) << 12) as DWord; + pub fn imm_j(self) -> u64 { + let imm_20 = ((self.0 & 0x8000_0000) as i32 as i64 >> (31 - 20)) as u64; + let imm_10_1 = ((self.0 >> 21 & 0x3ff) << 1) as u64; + let imm_11 = ((self.0 >> 20 & 1) << 11) as u64; + let imm_19_12 = ((self.0 >> 12 & 0xff) << 12) as u64; imm_20 | imm_10_1 | imm_11 | imm_19_12 } diff --git a/src/exceptions.rs b/src/exceptions.rs index 6bc21f2..cc18839 100644 --- a/src/exceptions.rs +++ b/src/exceptions.rs @@ -6,8 +6,6 @@ use int_enum::IntEnum; -use crate::consts::{Addr, DWord}; - #[repr(u8)] #[allow(dead_code)] #[derive(Debug, Clone, Copy, PartialEq, Eq, IntEnum)] @@ -43,7 +41,7 @@ impl ExceptionType { #[derive(Debug, Clone, Copy)] pub struct Exception { pub type_: ExceptionType, - pub value: DWord, + pub value: u64, } #[derive(Debug, Clone, Copy, PartialEq, Eq)] @@ -56,7 +54,7 @@ pub enum MemoryExceptionType { #[derive(Debug, Clone, Copy)] pub struct MemoryException { pub type_: MemoryExceptionType, - pub addr: Addr, + pub addr: u64, } impl MemoryException { diff --git a/src/execload.rs b/src/execload.rs index 6caa797..2b46599 100644 --- a/src/execload.rs +++ b/src/execload.rs @@ -14,9 +14,9 @@ use goblin::{ program_header::PT_LOAD, }, }; -use trve::{consts::Addr, mem::RAM_START}; +use trve::mem::RAM_START; -pub fn load>(path: P, ram: &mut [u8]) -> Result { +pub fn load>(path: P, ram: &mut [u8]) -> Result { let buf = fs::read(path)?; match Object::parse(&buf)? { diff --git a/src/gdb.rs b/src/gdb.rs index 2457d47..d781a6a 100644 --- a/src/gdb.rs +++ b/src/gdb.rs @@ -11,7 +11,6 @@ use std::{ }; use crate::{ - consts::{Addr, RegValue}, core::commands::CoreCmd, exceptions::{ExceptionType, MemoryExceptionType}, }; @@ -19,14 +18,14 @@ use crate::{ pub(crate) enum DebugCommand { GetRegs(oneshot::Sender), ReadMem { - addr: Addr, + addr: u64, len: u64, responder: oneshot::Sender, MemoryExceptionType>>, }, Step(oneshot::Sender), Continue(oneshot::Sender, oneshot::Receiver<()>), - SetBreakpoint(Addr), - RemoveBreakpoint(Addr), + SetBreakpoint(u64), + RemoveBreakpoint(u64), ExitDebugMode, } @@ -65,8 +64,8 @@ impl StopReason { } pub(crate) struct RegsResponse { - pub x_regs: [RegValue; 32], - pub pc: Addr, + pub x_regs: [u64; 32], + pub pc: u64, } pub fn run_stub(cmd_sender: mpsc::Sender) { diff --git a/src/instructions.rs b/src/instructions.rs index 99df830..2a2f6b0 100644 --- a/src/instructions.rs +++ b/src/instructions.rs @@ -10,7 +10,6 @@ mod macros; mod rvi; use crate::{ - consts::DWord, core::Core, decode::Instruction, exceptions::{ @@ -22,7 +21,7 @@ use crate::{ fn illegal(instr: Instruction) -> Result<(), Exception> { Err(Exception { type_: IllegalInstruction, - value: instr.0 as DWord, + value: instr.0 as u64, }) } diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs index 9f34fb1..424e9e4 100644 --- a/src/instructions/rvi.rs +++ b/src/instructions/rvi.rs @@ -4,7 +4,7 @@ // This file is part of TRVE (https://gitea.taitep.se/taitep/trve) // See LICENSE file in the project root for full license text. -use crate::{consts::RegValue, core::Core, decode::Instruction, exceptions::Exception}; +use crate::{core::Core, decode::Instruction, exceptions::Exception}; use std::ops::{BitAnd, BitOr, BitXor}; @@ -12,42 +12,38 @@ mod mem; pub use mem::*; -instr_op!(add, addi, RegValue::wrapping_add); -instr_op!( - addw, - addiw, - |a, b| RegValue::wrapping_add(a, b) as i32 as i64 as RegValue -); -instr_op_r!(sub, RegValue::wrapping_sub); -instr_op_r!(subw, |a, b| RegValue::wrapping_sub(a, b) as i32 as i64 - as RegValue); +instr_op!(add, addi, u64::wrapping_add); +instr_op!(addw, addiw, |a, b| u64::wrapping_add(a, b) as i32 as i64 + as u64); +instr_op_r!(sub, u64::wrapping_sub); +instr_op_r!(subw, |a, b| u64::wrapping_sub(a, b) as i32 as i64 as u64); -instr_op!(and, andi, RegValue::bitand); -instr_op!(or, ori, RegValue::bitor); -instr_op!(xor, xori, RegValue::bitxor); +instr_op!(and, andi, u64::bitand); +instr_op!(or, ori, u64::bitor); +instr_op!(xor, xori, u64::bitxor); instr_op!(sll, slli, |x, shamt| x << (shamt & 0b111111)); instr_op!( sllw, slliw, - |x, shamt| (x << (shamt & 0b11111)) as i32 as i64 as RegValue + |x, shamt| (x << (shamt & 0b11111)) as i32 as i64 as u64 ); instr_op!(srl, srli, |x, shamt| x >> (shamt & 0b111111)); instr_op!( srlw, srliw, - |x, shamt| (x >> (shamt & 0b11111)) as i32 as i64 as RegValue + |x, shamt| (x >> (shamt & 0b11111)) as i32 as i64 as u64 ); instr_op!(sra, srai, |x, shamt| (x as i64 >> (shamt & 0b111111)) - as RegValue); + as u64); instr_op!( sraw, sraiw, - |x, shamt| (x as i32 >> (shamt & 0b11111)) as i64 as RegValue + |x, shamt| (x as i32 >> (shamt & 0b11111)) as i64 as u64 ); -instr_op!(sltu, sltiu, |a, b| (a < b) as RegValue); -instr_op!(slt, slti, |a, b| ((a as i64) < (b as i64)) as RegValue); +instr_op!(sltu, sltiu, |a, b| (a < b) as u64); +instr_op!(slt, slti, |a, b| ((a as i64) < (b as i64)) as u64); pub fn lui(core: &mut Core, instr: Instruction) -> Result<(), Exception> { core.reg_write(instr.rd(), instr.imm_u()); diff --git a/src/instructions/rvi/mem.rs b/src/instructions/rvi/mem.rs index 071fa79..caa18e1 100644 --- a/src/instructions/rvi/mem.rs +++ b/src/instructions/rvi/mem.rs @@ -4,12 +4,7 @@ // This file is part of TRVE (https://gitea.taitep.se/taitep/trve) // See LICENSE file in the project root for full license text. -use crate::{ - consts::{Byte, DWord, HWord, Word}, - core::Core, - exceptions::Exception, - instructions::Instruction, -}; +use crate::{core::Core, exceptions::Exception, instructions::Instruction}; pub fn sd(core: &mut Core, instr: Instruction) -> Result<(), Exception> { let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); @@ -35,7 +30,7 @@ pub fn ld(core: &mut Core, instr: Instruction) -> Result<(), Exception> { pub fn sw(core: &mut Core, instr: Instruction) -> Result<(), Exception> { let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); - let value = core.reg_read(instr.rs2()) as Word; + let value = core.reg_read(instr.rs2()) as u32; core.mem .write_word(addr, value) .map_err(|e| e.to_exception_store())?; @@ -49,7 +44,7 @@ pub fn lw(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_word(addr) - .map_err(|e| e.to_exception_load())? as i32 as i64 as DWord, + .map_err(|e| e.to_exception_load())? as i32 as i64 as u64, ); core.advance_pc(); Ok(()) @@ -61,7 +56,7 @@ pub fn lwu(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_word(addr) - .map_err(|e| e.to_exception_load())? as DWord, + .map_err(|e| e.to_exception_load())? as u64, ); core.advance_pc(); Ok(()) @@ -69,7 +64,7 @@ pub fn lwu(core: &mut Core, instr: Instruction) -> Result<(), Exception> { pub fn sh(core: &mut Core, instr: Instruction) -> Result<(), Exception> { let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); - let value = core.reg_read(instr.rs2()) as HWord; + let value = core.reg_read(instr.rs2()) as u16; core.mem .write_hword(addr, value) .map_err(|e| e.to_exception_store())?; @@ -83,7 +78,7 @@ pub fn lh(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_hword(addr) - .map_err(|e| e.to_exception_load())? as i16 as i64 as DWord, + .map_err(|e| e.to_exception_load())? as i16 as i64 as u64, ); core.advance_pc(); Ok(()) @@ -95,7 +90,7 @@ pub fn lhu(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_hword(addr) - .map_err(|e| e.to_exception_load())? as DWord, + .map_err(|e| e.to_exception_load())? as u64, ); core.advance_pc(); Ok(()) @@ -103,7 +98,7 @@ pub fn lhu(core: &mut Core, instr: Instruction) -> Result<(), Exception> { pub fn sb(core: &mut Core, instr: Instruction) -> Result<(), Exception> { let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); - let value = core.reg_read(instr.rs2()) as Byte; + let value = core.reg_read(instr.rs2()) as u8; core.mem .write_byte(addr, value) .map_err(|e| e.to_exception_store())?; @@ -117,7 +112,7 @@ pub fn lb(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_byte(addr) - .map_err(|e| e.to_exception_load())? as i8 as i64 as DWord, + .map_err(|e| e.to_exception_load())? as i8 as i64 as u64, ); core.advance_pc(); Ok(()) @@ -129,7 +124,7 @@ pub fn lbu(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_byte(addr) - .map_err(|e| e.to_exception_load())? as DWord, + .map_err(|e| e.to_exception_load())? as u64, ); core.advance_pc(); Ok(()) diff --git a/src/lib.rs b/src/lib.rs index 6eda620..a74dffb 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,4 +1,3 @@ -pub mod consts; pub mod core; mod decode; pub mod exceptions; diff --git a/src/main.rs b/src/main.rs index 780534f..11330bd 100644 --- a/src/main.rs +++ b/src/main.rs @@ -9,7 +9,6 @@ use std::{path::PathBuf, sync::Arc, time::Duration}; use clap::Parser; use trve::{ - consts::{Addr, Byte, DWord, HWord, Word}, core::Core, exceptions::MemoryException, gdb, @@ -70,22 +69,22 @@ mod basic_uart; struct DbgOut; impl MemDeviceInterface for DbgOut { - fn write_dword(&self, addr: Addr, value: DWord) -> Result<(), MemoryException> { + fn write_dword(&self, addr: u64, value: u64) -> Result<(), MemoryException> { eprintln!("Wrote DWord {value:016x} to Debug-Out address {addr:x}"); Ok(()) } - fn write_word(&self, addr: Addr, value: Word) -> Result<(), MemoryException> { + fn write_word(&self, addr: u64, value: u32) -> Result<(), MemoryException> { eprintln!("Wrote Word {value:08x} to Debug-Out address {addr:x}"); Ok(()) } - fn write_hword(&self, addr: Addr, value: HWord) -> Result<(), MemoryException> { + fn write_hword(&self, addr: u64, value: u16) -> Result<(), MemoryException> { eprintln!("Wrote HWord {value:04x} to Debug-Out address {addr:x}"); Ok(()) } - fn write_byte(&self, addr: Addr, value: Byte) -> Result<(), MemoryException> { + fn write_byte(&self, addr: u64, value: u8) -> Result<(), MemoryException> { eprintln!("Wrote Byte {value:02x} to Debug-Out address {addr:x}"); Ok(()) } diff --git a/src/mem.rs b/src/mem.rs index 95a0eb2..e3cbe82 100644 --- a/src/mem.rs +++ b/src/mem.rs @@ -11,14 +11,11 @@ use std::sync::{ use memmap2::MmapMut; -use crate::{ - consts::{Addr, Byte, DWord, HWord, Word}, - exceptions::{MemoryException, MemoryExceptionType}, -}; +use crate::exceptions::{MemoryException, MemoryExceptionType}; pub type PageNum = usize; -pub const RAM_START: Addr = 0x8000_0000; +pub const RAM_START: u64 = 0x8000_0000; #[derive(Clone)] pub struct MemConfig { @@ -27,7 +24,7 @@ pub struct MemConfig { } impl MemConfig { - pub fn memory_mapping_type(&self, addr: Addr) -> Option { + pub fn memory_mapping_type(&self, addr: u64) -> Option { if addr >= RAM_START { Some(MemoryMappingType::RAM) } else { @@ -37,7 +34,7 @@ impl MemConfig { } } - pub fn read_dword(&self, addr: Addr) -> Result { + pub fn read_dword(&self, addr: u64) -> Result { if addr >= RAM_START { self.ram.read_dword(addr - RAM_START) } else { @@ -55,7 +52,7 @@ impl MemConfig { interface.read_dword(addr) } } - pub fn read_word(&self, addr: Addr) -> Result { + pub fn read_word(&self, addr: u64) -> Result { if addr >= RAM_START { self.ram.read_word(addr - RAM_START) } else { @@ -73,7 +70,7 @@ impl MemConfig { interface.read_word(addr) } } - pub fn read_hword(&self, addr: Addr) -> Result { + pub fn read_hword(&self, addr: u64) -> Result { if addr >= RAM_START { self.ram.read_hword(addr - RAM_START) } else { @@ -90,7 +87,7 @@ impl MemConfig { interface.read_hword(addr) } } - pub fn read_byte(&self, addr: Addr) -> Result { + pub fn read_byte(&self, addr: u64) -> Result { if addr >= RAM_START { self.ram.read_byte(addr - RAM_START) } else { @@ -102,7 +99,7 @@ impl MemConfig { } } - pub fn write_dword(&self, addr: Addr, value: DWord) -> Result<(), MemoryException> { + pub fn write_dword(&self, addr: u64, value: u64) -> Result<(), MemoryException> { if addr >= RAM_START { self.ram.write_dword(addr - RAM_START, value) } else { @@ -119,7 +116,7 @@ impl MemConfig { interface.write_dword(addr, value) } } - pub fn write_word(&self, addr: Addr, value: Word) -> Result<(), MemoryException> { + pub fn write_word(&self, addr: u64, value: u32) -> Result<(), MemoryException> { if addr >= RAM_START { self.ram.write_word(addr - RAM_START, value) } else { @@ -136,7 +133,7 @@ impl MemConfig { interface.write_word(addr, value) } } - pub fn write_hword(&self, addr: Addr, value: HWord) -> Result<(), MemoryException> { + pub fn write_hword(&self, addr: u64, value: u16) -> Result<(), MemoryException> { if addr >= RAM_START { self.ram.write_hword(addr - RAM_START, value) } else { @@ -153,7 +150,7 @@ impl MemConfig { interface.write_hword(addr, value) } } - pub fn write_byte(&self, addr: Addr, value: Byte) -> Result<(), MemoryException> { + pub fn write_byte(&self, addr: u64, value: u8) -> Result<(), MemoryException> { if addr >= RAM_START { self.ram.write_byte(addr - RAM_START, value) } else { @@ -165,7 +162,7 @@ impl MemConfig { } } - pub fn get_atomic_dword(&self, addr: Addr) -> Result<&AtomicU64, MemoryException> { + pub fn get_atomic_dword(&self, addr: u64) -> Result<&AtomicU64, MemoryException> { if !addr.is_multiple_of(8) { return Err(MemoryException { type_: MemoryExceptionType::AddressMisaligned, @@ -184,7 +181,7 @@ impl MemConfig { }) } } - pub fn get_atomic_word(&self, addr: Addr) -> Result<&AtomicU32, MemoryException> { + pub fn get_atomic_word(&self, addr: u64) -> Result<&AtomicU32, MemoryException> { if !addr.is_multiple_of(4) { return Err(MemoryException { type_: MemoryExceptionType::AddressMisaligned, @@ -262,14 +259,14 @@ impl Ram { } #[inline] - pub fn read_dword(&self, addr: Addr) -> Result { + pub fn read_dword(&self, addr: u64) -> Result { if !addr.is_multiple_of(8) { let high_word_addr = addr.wrapping_add(4); let low_word = self.read_byte(addr)?; let high_word = self.read_byte(high_word_addr)?; - return Ok((low_word as DWord) | (high_word as DWord) << 32); + return Ok((low_word as u64) | (high_word as u64) << 32); } let index = (addr / 8) as usize; @@ -284,14 +281,14 @@ impl Ram { .load(Relaxed)) } #[inline] - pub fn read_word(&self, addr: Addr) -> Result { + pub fn read_word(&self, addr: u64) -> Result { if !addr.is_multiple_of(4) { let high_hword_addr = addr.wrapping_add(2); let low_hword = self.read_hword(addr)?; let high_hword = self.read_hword(high_hword_addr)?; - return Ok((low_hword as Word) | (high_hword as Word) << 16); + return Ok((low_hword as u32) | (high_hword as u32) << 16); } let index = (addr / 4) as usize; @@ -306,14 +303,14 @@ impl Ram { .load(Relaxed)) } #[inline] - pub fn read_hword(&self, addr: Addr) -> Result { + pub fn read_hword(&self, addr: u64) -> Result { if !addr.is_multiple_of(2) { let high_byte_addr = addr.wrapping_add(1); let low_byte = self.read_byte(addr)?; let high_byte = self.read_byte(high_byte_addr)?; - return Ok((low_byte as HWord) | (high_byte as HWord) << 8); + return Ok((low_byte as u16) | (high_byte as u16) << 8); } let index = (addr / 2) as usize; @@ -328,7 +325,7 @@ impl Ram { .load(Relaxed)) } #[inline] - pub fn read_byte(&self, addr: Addr) -> Result { + pub fn read_byte(&self, addr: u64) -> Result { Ok(self .buf_atomic() .get(addr as usize) @@ -340,10 +337,10 @@ impl Ram { } #[inline] - pub fn write_dword(&self, addr: Addr, value: DWord) -> Result<(), MemoryException> { + pub fn write_dword(&self, addr: u64, value: u64) -> Result<(), MemoryException> { if !addr.is_multiple_of(8) { - let low_word = value as Word; - let high_word = (value >> 32) as Word; + let low_word = value as u32; + let high_word = (value >> 32) as u32; let high_word_address = addr.wrapping_add(4); @@ -365,10 +362,10 @@ impl Ram { Ok(()) } #[inline] - pub fn write_word(&self, addr: Addr, value: Word) -> Result<(), MemoryException> { + pub fn write_word(&self, addr: u64, value: u32) -> Result<(), MemoryException> { if !addr.is_multiple_of(4) { - let low_hword = value as HWord; - let high_hword = (value >> 16) as HWord; + let low_hword = value as u16; + let high_hword = (value >> 16) as u16; let high_hword_address = addr.wrapping_add(2); @@ -390,10 +387,10 @@ impl Ram { Ok(()) } #[inline] - pub fn write_hword(&self, addr: Addr, value: HWord) -> Result<(), MemoryException> { + pub fn write_hword(&self, addr: u64, value: u16) -> Result<(), MemoryException> { if !addr.is_multiple_of(2) { - let low_byte = value as Byte; - let high_byte = (value >> 8) as Byte; + let low_byte = value as u8; + let high_byte = (value >> 8) as u8; let high_byte_address = addr.wrapping_add(1); @@ -415,7 +412,7 @@ impl Ram { Ok(()) } #[inline] - pub fn write_byte(&self, addr: Addr, value: Byte) -> Result<(), MemoryException> { + pub fn write_byte(&self, addr: u64, value: u8) -> Result<(), MemoryException> { self.buf_atomic() .get(addr as usize) .ok_or(MemoryException { @@ -437,7 +434,7 @@ const MMIO_SECOND_LEVEL_ENTRIES: usize = MMIO_ROOT_PAGE_SIZE / MMIO_SECOND_LEVEL pub struct MmioRoot(Box<[Option; MMIO_ROOT_ENTRIES]>); impl MmioRoot { - pub fn insert(&mut self, base_addr: Addr, interface: Arc) { + pub fn insert(&mut self, base_addr: u64, interface: Arc) { assert!(base_addr.is_multiple_of(MMIO_SECOND_LEVEL_PAGE_SIZE as u64)); assert!(base_addr < RAM_START); @@ -452,7 +449,7 @@ impl MmioRoot { } } - pub fn insert_full(&mut self, base_addr: Addr, interface: Arc) { + pub fn insert_full(&mut self, base_addr: u64, interface: Arc) { assert!(base_addr.is_multiple_of(MMIO_ROOT_PAGE_SIZE as u64)); assert!(base_addr < RAM_START); @@ -461,7 +458,7 @@ impl MmioRoot { self.0[page_id] = Some(MmioSecondLevel::Interface(interface)); } - fn get_device(&self, addr: Addr) -> Option<(Arc, Addr)> { + fn get_device(&self, addr: u64) -> Option<(Arc, u64)> { debug_assert!(addr < RAM_START); let page_id = addr as usize / MMIO_SECOND_LEVEL_PAGE_SIZE; @@ -469,10 +466,10 @@ impl MmioRoot { self.0[root_page_id] .as_ref() - .and_then(|s| s.get_device(addr % MMIO_ROOT_PAGE_SIZE as Addr)) + .and_then(|s| s.get_device(addr % MMIO_ROOT_PAGE_SIZE as u64)) } - fn crosses_boundary(&self, addr: Addr, size: Addr) -> bool { + fn crosses_boundary(&self, addr: u64, size: u64) -> bool { if addr >= RAM_START { return false; } @@ -514,12 +511,12 @@ enum MmioSecondLevel { } impl MmioSecondLevel { - fn get_device(&self, addr: Addr) -> Option<(Arc, Addr)> { + fn get_device(&self, addr: u64) -> Option<(Arc, u64)> { let page_id = addr as usize / MMIO_SECOND_LEVEL_PAGE_SIZE; match self { Self::SubTable(t) => t[page_id] .as_ref() - .map(|i| (i.clone(), addr % MMIO_SECOND_LEVEL_PAGE_SIZE as Addr)), + .map(|i| (i.clone(), addr % MMIO_SECOND_LEVEL_PAGE_SIZE as u64)), Self::Interface(i) => Some((i.clone(), addr)), } @@ -534,50 +531,50 @@ impl Default for MmioSecondLevel { #[allow(unused_variables)] pub trait MemDeviceInterface { - fn write_dword(&self, addr: Addr, value: DWord) -> Result<(), MemoryException> { + fn write_dword(&self, addr: u64, value: u64) -> Result<(), MemoryException> { Err(MemoryException { type_: MemoryExceptionType::AccessFault, addr, }) } - fn write_word(&self, addr: Addr, value: Word) -> Result<(), MemoryException> { + fn write_word(&self, addr: u64, value: u32) -> Result<(), MemoryException> { Err(MemoryException { type_: MemoryExceptionType::AccessFault, addr, }) } - fn write_hword(&self, addr: Addr, value: HWord) -> Result<(), MemoryException> { + fn write_hword(&self, addr: u64, value: u16) -> Result<(), MemoryException> { Err(MemoryException { type_: MemoryExceptionType::AccessFault, addr, }) } - fn write_byte(&self, addr: Addr, value: Byte) -> Result<(), MemoryException> { + fn write_byte(&self, addr: u64, value: u8) -> Result<(), MemoryException> { Err(MemoryException { type_: MemoryExceptionType::AccessFault, addr, }) } - fn read_dword(&self, addr: Addr) -> Result { + fn read_dword(&self, addr: u64) -> Result { Err(MemoryException { type_: MemoryExceptionType::AccessFault, addr, }) } - fn read_word(&self, addr: Addr) -> Result { + fn read_word(&self, addr: u64) -> Result { Err(MemoryException { type_: MemoryExceptionType::AccessFault, addr, }) } - fn read_hword(&self, addr: Addr) -> Result { + fn read_hword(&self, addr: u64) -> Result { Err(MemoryException { type_: MemoryExceptionType::AccessFault, addr, }) } - fn read_byte(&self, addr: Addr) -> Result { + fn read_byte(&self, addr: u64) -> Result { Err(MemoryException { type_: MemoryExceptionType::AccessFault, addr,