Implement LD and BNE
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@@ -35,11 +35,13 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Option<Instr
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// LOAD
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// LOAD
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0b000 => Some(rvi::lb(core, instr)),
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0b000 => Some(rvi::lb(core, instr)),
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0b100 => Some(rvi::lbu(core, instr)),
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0b100 => Some(rvi::lbu(core, instr)),
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0b011 => Some(rvi::ld(core, instr)),
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_ => None,
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_ => None,
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},
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},
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0b11000 => match instr.funct3() {
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0b11000 => match instr.funct3() {
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// BRANCH
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// BRANCH
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0b000 => Some(rvi::beq(core, instr)),
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0b000 => Some(rvi::beq(core, instr)),
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0b001 => Some(rvi::bne(core, instr)),
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_ => None,
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_ => None,
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},
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},
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0b01101 => Some(rvi::lui(core, instr)),
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0b01101 => Some(rvi::lui(core, instr)),
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@@ -61,6 +61,26 @@ pub fn sd(core: &mut Core, instr: Instruction) -> InstructionResult {
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}
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}
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}
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}
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pub fn ld(core: &mut Core, instr: Instruction) -> InstructionResult {
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let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
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if !addr.is_multiple_of(std::mem::size_of::<DWord>() as Addr) {
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return InstructionResult::Exception(());
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}
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let page = (addr / 4096) as PageNum;
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let offset = (addr / 8 & ((4096 / 8 as Addr) - 1)) as u16;
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match core.mem.read_dword(page, offset) {
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Ok(x) => {
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core.reg_write(instr.rd(), x);
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core.advance_pc();
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InstructionResult::Normal
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}
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Err(_) => InstructionResult::Exception(()),
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}
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}
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pub fn sb(core: &mut Core, instr: Instruction) -> InstructionResult {
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pub fn sb(core: &mut Core, instr: Instruction) -> InstructionResult {
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let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
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let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
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@@ -145,6 +165,16 @@ pub fn beq(core: &mut Core, instr: Instruction) -> InstructionResult {
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InstructionResult::Normal
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InstructionResult::Normal
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}
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}
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pub fn bne(core: &mut Core, instr: Instruction) -> InstructionResult {
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if core.reg_read(instr.rs1()) != core.reg_read(instr.rs2()) {
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core.pc = core.pc.wrapping_add(instr.imm_b());
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} else {
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core.advance_pc();
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}
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InstructionResult::Normal
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}
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pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
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pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
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core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());
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core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());
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