From 209e44ae64a1af10063b1c589377e136c644ec8f Mon Sep 17 00:00:00 2001 From: taitep Date: Sun, 21 Dec 2025 21:00:25 +0100 Subject: [PATCH] Implement LD and BNE --- src/instructions.rs | 2 ++ src/instructions/rvi.rs | 30 ++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/src/instructions.rs b/src/instructions.rs index e72dfb5..a2edc53 100644 --- a/src/instructions.rs +++ b/src/instructions.rs @@ -35,11 +35,13 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Option Some(rvi::lb(core, instr)), 0b100 => Some(rvi::lbu(core, instr)), + 0b011 => Some(rvi::ld(core, instr)), _ => None, }, 0b11000 => match instr.funct3() { // BRANCH 0b000 => Some(rvi::beq(core, instr)), + 0b001 => Some(rvi::bne(core, instr)), _ => None, }, 0b01101 => Some(rvi::lui(core, instr)), diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs index 239ae98..f182e88 100644 --- a/src/instructions/rvi.rs +++ b/src/instructions/rvi.rs @@ -61,6 +61,26 @@ pub fn sd(core: &mut Core, instr: Instruction) -> InstructionResult { } } +pub fn ld(core: &mut Core, instr: Instruction) -> InstructionResult { + let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); + + if !addr.is_multiple_of(std::mem::size_of::() as Addr) { + return InstructionResult::Exception(()); + } + + let page = (addr / 4096) as PageNum; + let offset = (addr / 8 & ((4096 / 8 as Addr) - 1)) as u16; + + match core.mem.read_dword(page, offset) { + Ok(x) => { + core.reg_write(instr.rd(), x); + core.advance_pc(); + InstructionResult::Normal + } + Err(_) => InstructionResult::Exception(()), + } +} + pub fn sb(core: &mut Core, instr: Instruction) -> InstructionResult { let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); @@ -145,6 +165,16 @@ pub fn beq(core: &mut Core, instr: Instruction) -> InstructionResult { InstructionResult::Normal } +pub fn bne(core: &mut Core, instr: Instruction) -> InstructionResult { + if core.reg_read(instr.rs1()) != core.reg_read(instr.rs2()) { + core.pc = core.pc.wrapping_add(instr.imm_b()); + } else { + core.advance_pc(); + } + + InstructionResult::Normal +} + pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult { core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());