taitep/trve
1
1
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Implement AND and improve formatting and ordering in rvi.rs

Browse Source
This commit is contained in:
taitep
2025-12-22 19:25:19 +01:00
parent ff161a69e6
commit 1ddda6614a
2 changed files with 14 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/instructions.rs
View File

@@ -16,6 +16,7 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Option<Instr
0b01100 => match (instr.funct7(), instr.funct3()) { 0b01100 => match (instr.funct7(), instr.funct3()) {
// OP // OP
(0b0000000, 0b000) => Some(rvi::add(core, instr)), (0b0000000, 0b000) => Some(rvi::add(core, instr)),
(0b0000000, 0b111) => Some(rvi::and(core, instr)),
_ => None, _ => None,
}, },
0b00100 => match instr.funct3() { 0b00100 => match instr.funct3() {

26
src/instructions/rvi.rs
View File

@@ -26,27 +26,35 @@ pub fn addi(core: &mut Core, instr: Instruction) -> InstructionResult {
instr.rd(), instr.rd(),
core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()), core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()),
); );
core.advance_pc(); core.advance_pc();
InstructionResult::Normal InstructionResult::Normal
} }
pub fn addiw(core: &mut Core, instr: Instruction) -> InstructionResult { pub fn addiw(core: &mut Core, instr: Instruction) -> InstructionResult {
let res = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()) as i32; let res = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()) as i32;
core.reg_write(instr.rd(), res as i64 as u64); core.reg_write(instr.rd(), res as i64 as u64);
core.advance_pc(); core.advance_pc();
InstructionResult::Normal
}
pub fn and(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(
instr.rd(),
core.reg_read(instr.rs1()) & core.reg_read(instr.rs2()),
);
core.advance_pc();
InstructionResult::Normal InstructionResult::Normal
} }
pub fn andi(core: &mut Core, instr: Instruction) -> InstructionResult { pub fn andi(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(instr.rd(), core.reg_read(instr.rs1()) & instr.imm_i()); core.reg_write(instr.rd(), core.reg_read(instr.rs1()) & instr.imm_i());
core.advance_pc(); core.advance_pc();
InstructionResult::Normal
}
pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());
core.advance_pc();
InstructionResult::Normal InstructionResult::Normal
} }
@@ -184,11 +192,3 @@ pub fn bne(core: &mut Core, instr: Instruction) -> InstructionResult {
InstructionResult::Normal InstructionResult::Normal
} }
pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());
core.advance_pc();
InstructionResult::Normal
}