diff --git a/src/instructions.rs b/src/instructions.rs
index c9c1c52..3096ed0 100644
--- a/src/instructions.rs
+++ b/src/instructions.rs
@@ -16,6 +16,7 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Option<Instr
         0b01100 => match (instr.funct7(), instr.funct3()) {
             // OP
             (0b0000000, 0b000) => Some(rvi::add(core, instr)),
+            (0b0000000, 0b111) => Some(rvi::and(core, instr)),
             _ => None,
         },
         0b00100 => match instr.funct3() {
diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs
index 608b1ae..395fe8e 100644
--- a/src/instructions/rvi.rs
+++ b/src/instructions/rvi.rs
@@ -26,27 +26,35 @@ pub fn addi(core: &mut Core, instr: Instruction) -> InstructionResult {
         instr.rd(),
         core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()),
     );
-
     core.advance_pc();
-
     InstructionResult::Normal
 }
 
 pub fn addiw(core: &mut Core, instr: Instruction) -> InstructionResult {
     let res = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()) as i32;
-
     core.reg_write(instr.rd(), res as i64 as u64);
-
     core.advance_pc();
+    InstructionResult::Normal
+}
 
+pub fn and(core: &mut Core, instr: Instruction) -> InstructionResult {
+    core.reg_write(
+        instr.rd(),
+        core.reg_read(instr.rs1()) & core.reg_read(instr.rs2()),
+    );
+    core.advance_pc();
     InstructionResult::Normal
 }
 
 pub fn andi(core: &mut Core, instr: Instruction) -> InstructionResult {
     core.reg_write(instr.rd(), core.reg_read(instr.rs1()) & instr.imm_i());
-
     core.advance_pc();
+    InstructionResult::Normal
+}
 
+pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
+    core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());
+    core.advance_pc();
     InstructionResult::Normal
 }
 
@@ -184,11 +192,3 @@ pub fn bne(core: &mut Core, instr: Instruction) -> InstructionResult {
 
     InstructionResult::Normal
 }
-
-pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
-    core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());
-
-    core.advance_pc();
-
-    InstructionResult::Normal
-}