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taitep
2025-10-14 18:22:09 +02:00
parent 7a519924cb
commit 19568f855e
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src/instructions/rvi.rs
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@@ -29,6 +29,7 @@ fn addi(core: &mut Core, instr: Instruction) -> InstructionResult {
InstructionResult::Normal InstructionResult::Normal
} }
// TODO: Support misaligned memory access
fn sd(core: &mut Core, instr: Instruction) -> InstructionResult { fn sd(core: &mut Core, instr: Instruction) -> InstructionResult {
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());