diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs
index 24d45a1..f82f1b3 100644
--- a/src/instructions/rvi.rs
+++ b/src/instructions/rvi.rs
@@ -29,6 +29,7 @@ fn addi(core: &mut Core, instr: Instruction) -> InstructionResult {
     InstructionResult::Normal
 }
 
+// TODO: Support misaligned memory access
 fn sd(core: &mut Core, instr: Instruction) -> InstructionResult {
     let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());