91 lines
2.6 KiB
Rust
91 lines
2.6 KiB
Rust
// Copyright (c) 2025 taitep
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// SPDX-License-Identifier: MIT
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//
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// This file is part of TRVE (https://gitea.taitep.se/taitep/trve)
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// See LICENSE file in the project root for full license text.
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use crate::{
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consts::{Addr, DWord},
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core::{Core, InstructionResult},
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decode::Instruction,
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mem::PageNum,
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};
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pub fn addi(core: &mut Core, instr: Instruction) -> InstructionResult {
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core.reg_write(
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instr.rd(),
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core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()),
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);
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core.pc = core.pc.wrapping_add(4);
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InstructionResult::Normal
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}
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pub fn addiw(core: &mut Core, instr: Instruction) -> InstructionResult {
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let res = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()) as i32;
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core.reg_write(instr.rd(), res as i64 as u64);
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core.pc = core.pc.wrapping_add(4);
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InstructionResult::Normal
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}
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// TODO: Support misaligned memory access
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pub fn sd(core: &mut Core, instr: Instruction) -> InstructionResult {
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let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
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if !addr.is_multiple_of(std::mem::size_of::<DWord>() as Addr) {
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return InstructionResult::Exception(());
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}
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let page = (addr / 4096) as PageNum;
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let offset = (addr / 8 & ((4096 / 8 as Addr) - 1)) as u16;
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let value = core.reg_read(instr.rs2());
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match core.mem.write_dword(page, offset, value) {
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Ok(_) => {
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core.pc = core.pc.wrapping_add(4);
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InstructionResult::Normal
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}
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Err(_) => InstructionResult::Exception(()),
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}
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}
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pub fn sb(core: &mut Core, instr: Instruction) -> InstructionResult {
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let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
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let page = (addr / 4096) as PageNum;
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let offset = (addr & (4096 as Addr - 1)) as u16;
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let value = core.reg_read(instr.rs2()) as u8;
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match core.mem.write_byte(page, offset, value) {
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Ok(_) => {
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core.pc = core.pc.wrapping_add(4);
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InstructionResult::Normal
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}
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Err(_) => InstructionResult::Exception(()),
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}
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}
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pub fn lui(core: &mut Core, instr: Instruction) -> InstructionResult {
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core.reg_write(instr.rd(), instr.imm_u());
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core.pc = core.pc.wrapping_add(4);
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InstructionResult::Normal
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}
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pub fn jal(core: &mut Core, instr: Instruction) -> InstructionResult {
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core.reg_write(instr.rd(), core.pc);
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core.pc = core.pc.wrapping_add(instr.imm_j());
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InstructionResult::Normal
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}
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pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
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core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());
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core.pc = core.pc.wrapping_add(4);
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InstructionResult::Normal
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}
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