Implement LW

src/core.rs

@@ -53,6 +53,11 @@ impl Core {
                 }
             };
 
+            if instr == 0 {
+                eprintln!("Executing 0 instruction at {:X}", self.pc);
+                break;
+            }
+
             assert_eq!(instr & 3, 3, "Compressed instructions not supported");
 
             let instr = Instruction(instr);
@@ -73,7 +78,7 @@ impl Core {
                     }
                 }
             } else {
-                eprintln!("Invalid Instruction 0x{:08x} 0b{:032b}", instr.0, instr.0);
+                eprintln!("Invalid Instruction {:08x} at PC: {:x}", instr.0, self.pc);
                 break;
             }
         }

src/instructions.rs

@@ -44,6 +44,8 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Option<Instr
             // LOAD
             0b000 => Some(rvi::lb(core, instr)),
             0b100 => Some(rvi::lbu(core, instr)),
+            0b001 => Some(rvi::lh(core, instr)),
+            0b010 => Some(rvi::lw(core, instr)),
             0b011 => Some(rvi::ld(core, instr)),
             _ => None,
         },
@@ -51,6 +53,8 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Option<Instr
             // BRANCH
             0b000 => Some(rvi::beq(core, instr)),
             0b001 => Some(rvi::bne(core, instr)),
+            0b110 => Some(rvi::bltu(core, instr)),
+            0b111 => Some(rvi::bgeu(core, instr)),
             _ => None,
         },
         0b01101 => Some(rvi::lui(core, instr)),

src/instructions/rvi.rs

@@ -122,3 +122,23 @@ pub fn bne(core: &mut Core, instr: Instruction) -> InstructionResult {
 
     InstructionResult::Normal
 }
+
+pub fn bgeu(core: &mut Core, instr: Instruction) -> InstructionResult {
+    if core.reg_read(instr.rs1()) >= core.reg_read(instr.rs2()) {
+        core.pc = core.pc.wrapping_add(instr.imm_b());
+    } else {
+        core.advance_pc();
+    }
+
+    InstructionResult::Normal
+}
+
+pub fn bltu(core: &mut Core, instr: Instruction) -> InstructionResult {
+    if core.reg_read(instr.rs1()) < core.reg_read(instr.rs2()) {
+        core.pc = core.pc.wrapping_add(instr.imm_b());
+    } else {
+        core.advance_pc();
+    }
+
+    InstructionResult::Normal
+}

src/instructions/rvi/mem.rs

@@ -1,5 +1,5 @@
 use crate::{
-    consts::{Addr, Byte, DWord, Word},
+    consts::{Addr, Byte, DWord, HWord, Word},
     core::Core,
     instructions::{Instruction, InstructionResult},
     mem::PageNum,
@@ -66,6 +66,46 @@ pub fn sw(core: &mut Core, instr: Instruction) -> InstructionResult {
     }
 }
 
+pub fn lw(core: &mut Core, instr: Instruction) -> InstructionResult {
+    let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
+
+    if !addr.is_multiple_of(std::mem::size_of::<Word>() as Addr) {
+        return InstructionResult::Exception(());
+    }
+
+    let page = (addr / 4096) as PageNum;
+    let offset = (addr / 4 & ((4096 / 4 as Addr) - 1)) as u16;
+
+    match core.mem.read_word(page, offset) {
+        Ok(x) => {
+            core.reg_write(instr.rd(), x as i32 as i64 as DWord);
+            core.advance_pc();
+            InstructionResult::Normal
+        }
+        Err(_) => InstructionResult::Exception(()),
+    }
+}
+
+pub fn lh(core: &mut Core, instr: Instruction) -> InstructionResult {
+    let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
+
+    if !addr.is_multiple_of(std::mem::size_of::<HWord>() as Addr) {
+        return InstructionResult::Exception(());
+    }
+
+    let page = (addr / 4096) as PageNum;
+    let offset = (addr / 2 & ((4096 / 2 as Addr) - 1)) as u16;
+
+    match core.mem.read_hword(page, offset) {
+        Ok(x) => {
+            core.reg_write(instr.rd(), x as i16 as i64 as DWord);
+            core.advance_pc();
+            InstructionResult::Normal
+        }
+        Err(_) => InstructionResult::Exception(()),
+    }
+}
+
 pub fn sb(core: &mut Core, instr: Instruction) -> InstructionResult {
     let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());