Implement BLT

src/core.rs

@@ -49,12 +49,13 @@ impl Core {
                 Ok(i) => i,
                 Err(_) => {
                     eprintln!("Memory access fault while fetching instruction");
+                    eprintln!("PC: {:x}", self.pc);
                     break;
                 }
             };
 
             if instr == 0 {
-                eprintln!("Executing 0 instruction at {:X}", self.pc);
+                eprintln!("Executing 0 instruction at {:x}", self.pc);
                 break;
             }
 
@@ -69,7 +70,7 @@ impl Core {
                     InstructionResult::Normal => {}
                     InstructionResult::Exception(_e) => {
                         eprintln!("Exception from instruction");
-                        eprintln!("PC: {:016X}, instr: {:08X}", self.pc, instr.0);
+                        eprintln!("PC: {:016x}, instr: {:08x}", self.pc, instr.0);
                         break;
                     }
                     InstructionResult::Pause => {

src/decode.rs

@@ -57,7 +57,7 @@ impl Instruction {
 
     #[inline]
     pub fn imm_s(self) -> DWord {
-        (self.0 as i32 as i64 >> (25 - 5) & (0x7f << 5)) as DWord | (self.0 >> 7 & 0b1111) as DWord
+        (self.0 as i32 as i64 >> (25 - 5) & (0x7f << 5)) as DWord | (self.0 >> 7 & 0b11111) as DWord
     }
 
     #[inline]

src/instructions.rs

@@ -53,6 +53,7 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Option<Instr
             // BRANCH
             0b000 => Some(rvi::beq(core, instr)),
             0b001 => Some(rvi::bne(core, instr)),
+            0b100 => Some(rvi::blt(core, instr)),
             0b110 => Some(rvi::bltu(core, instr)),
             0b111 => Some(rvi::bgeu(core, instr)),
             _ => None,

src/instructions/rvi.rs

@@ -93,12 +93,19 @@ pub fn auipc(core: &mut Core, instr: Instruction) -> InstructionResult {
 
 pub fn jal(core: &mut Core, instr: Instruction) -> InstructionResult {
     core.reg_write(instr.rd(), core.pc.wrapping_add(4));
+    eprintln!("set x{} to {:x}", instr.rd(), core.pc.wrapping_add(4));
     core.pc = core.pc.wrapping_add(instr.imm_j());
     InstructionResult::Normal
 }
 
 pub fn jalr(core: &mut Core, instr: Instruction) -> InstructionResult {
     core.reg_write(instr.rd(), core.pc.wrapping_add(4));
+    eprintln!(
+        "origin: {:x}, reg: x{}={:x}",
+        core.pc,
+        instr.rs1(),
+        core.reg_read(instr.rs1())
+    );
     core.pc = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
     InstructionResult::Normal
 }
@@ -123,6 +130,16 @@ pub fn bne(core: &mut Core, instr: Instruction) -> InstructionResult {
     InstructionResult::Normal
 }
 
+pub fn blt(core: &mut Core, instr: Instruction) -> InstructionResult {
+    if (core.reg_read(instr.rs1()) as i64) < (core.reg_read(instr.rs2()) as i64) {
+        core.pc = core.pc.wrapping_add(instr.imm_b());
+    } else {
+        core.advance_pc();
+    }
+
+    InstructionResult::Normal
+}
+
 pub fn bgeu(core: &mut Core, instr: Instruction) -> InstructionResult {
     if core.reg_read(instr.rs1()) >= core.reg_read(instr.rs2()) {
         core.pc = core.pc.wrapping_add(instr.imm_b());

src/main.rs

@@ -6,7 +6,6 @@
 
 use std::{
     env,
-    error::Error,
     fs::File,
     io::{self, Read},
     sync::Arc,