Implement ANDI and BEQ

Cargo.lock

@@ -19,7 +19,7 @@ dependencies = [
 
 [[package]]
 name = "trve"
-version = "0.1.0"
+version = "0.0.0"
 dependencies = [
  "memmap2",
 ]

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "trve"
-version = "0.1.0"
+version = "0.0.0"
 edition = "2024"
 
 [dependencies]

src/basic_uart.rs

@@ -0,0 +1,153 @@
+use std::collections::VecDeque;
+use std::io::{Read, stdin};
+use std::sync::{Arc, Mutex};
+use std::thread;
+use std::time::Duration;
+
+use trve::consts::{Byte, DWord, HWord, Word};
+use trve::mem::{MemAccessFault, MemDeviceInterface, PageNum};
+
+/// byte 0: rx/tx
+/// byte 1: status (------rt, r=rxready, t=txready)/none
+pub struct BasicUart {
+    buffers: Mutex<UartBuffers>,
+}
+
+struct UartBuffers {
+    rx: VecDeque<u8>,
+    tx: VecDeque<u8>,
+}
+
+impl BasicUart {
+    pub fn new() -> Self {
+        BasicUart {
+            buffers: Mutex::new(UartBuffers {
+                rx: VecDeque::new(),
+                tx: VecDeque::new(),
+            }),
+        }
+    }
+
+    pub fn spawn_poller(self, poll_interval: Duration) -> Arc<Self> {
+        let shared = Arc::new(self);
+
+        let uart_clone = shared.clone();
+
+        thread::spawn(move || {
+            loop {
+                uart_clone.poll();
+                thread::sleep(poll_interval);
+            }
+        });
+
+        shared
+    }
+
+    fn write(&self, byte: u8) {
+        let mut bufs = self.buffers.lock().unwrap();
+        bufs.tx.push_back(byte);
+    }
+
+    fn read(&self) -> u8 {
+        let mut bufs = self.buffers.lock().unwrap();
+        bufs.rx.pop_front().unwrap_or(0)
+    }
+
+    fn can_read(&self) -> bool {
+        let bufs = self.buffers.lock().unwrap();
+        !bufs.rx.is_empty()
+    }
+
+    pub fn poll(&self) {
+        let mut bufs = self.buffers.lock().unwrap();
+
+        while let Some(byte) = bufs.tx.pop_front() {
+            print!("{}", byte as char);
+        }
+
+        let mut buffer = [0u8; 1];
+        if let Ok(n) = stdin().read(&mut buffer) {
+            if n > 0 {
+                bufs.rx.push_back(buffer[0]);
+            }
+        }
+    }
+}
+
+impl MemDeviceInterface for BasicUart {
+    fn write_dword(
+        &self,
+        _page: PageNum,
+        _offset: u16,
+        _value: DWord,
+    ) -> Result<(), MemAccessFault> {
+        Err(MemAccessFault)
+    }
+
+    fn write_word(&self, _page: PageNum, _offset: u16, _value: Word) -> Result<(), MemAccessFault> {
+        Err(MemAccessFault)
+    }
+
+    fn write_hword(
+        &self,
+        _page: PageNum,
+        _offset: u16,
+        _value: HWord,
+    ) -> Result<(), MemAccessFault> {
+        Err(MemAccessFault)
+    }
+
+    fn write_byte(&self, page: PageNum, offset: u16, value: Byte) -> Result<(), MemAccessFault> {
+        if page > 0 {
+            return Err(MemAccessFault);
+        }
+
+        match offset {
+            0 => {
+                self.write(value);
+                Ok(())
+            }
+            _ => Err(MemAccessFault),
+        }
+    }
+
+    fn read_dword(&self, _page: PageNum, _offset: u16) -> Result<DWord, MemAccessFault> {
+        Err(MemAccessFault)
+    }
+
+    fn read_word(&self, _page: PageNum, _offset: u16) -> Result<Word, MemAccessFault> {
+        Err(MemAccessFault)
+    }
+
+    fn read_hword(&self, _page: PageNum, _offset: u16) -> Result<HWord, MemAccessFault> {
+        Err(MemAccessFault)
+    }
+
+    fn read_byte(&self, page: PageNum, offset: u16) -> Result<Byte, MemAccessFault> {
+        if page > 0 {
+            return Err(MemAccessFault);
+        }
+
+        match offset {
+            0 => Ok(self.read()),
+            1 => Ok(1 | (self.can_read() as u8) << 1),
+            _ => Err(MemAccessFault),
+        }
+    }
+
+    fn get_atomic_word(
+        &self,
+        _page: PageNum,
+        _offset: u16,
+    ) -> Result<&std::sync::atomic::AtomicU32, MemAccessFault> {
+        Err(MemAccessFault)
+    }
+
+    fn get_atomic_dword(
+        &self,
+        _page: PageNum,
+        _offset: u16,
+    ) -> Result<&std::sync::atomic::AtomicU64, MemAccessFault> {
+        Err(MemAccessFault)
+    }
+}

src/core.rs

@@ -92,4 +92,8 @@ impl Core {
         }
         self.x_regs[id as usize] = value;
     }
+
+    pub(crate) fn advance_pc(&mut self) {
+        self.pc = self.pc.wrapping_add(4);
+    }
 }

src/decode.rs

@@ -52,12 +52,12 @@ impl Instruction {
 
     #[inline]
     pub fn imm_i(self) -> DWord {
-        (self.0 as i64 >> 20) as DWord
+        (self.0 as i32 as i64 >> 20) as DWord
     }
 
     #[inline]
     pub fn imm_s(self) -> DWord {
-        (self.0 as i64 >> (25 - 5) & (0x7f << 5)) as DWord | (self.0 >> 7 & 0b1111) as DWord
+        (self.0 as i32 as i64 >> (25 - 5) & (0x7f << 5)) as DWord | (self.0 >> 7 & 0b1111) as DWord
     }
 
     #[inline]
@@ -88,12 +88,12 @@ impl Instruction {
     // The following are AFAIK only used for shift by immediate operations
 
     #[inline]
-    fn funct6(self) -> u8 {
+    pub fn funct6(self) -> u8 {
         (self.0 >> 26 & 0x3f) as u8
     }
 
     #[inline]
-    fn imm_shamt(self) -> usize {
+    pub fn imm_shamt(self) -> usize {
         (self.0 >> 20 & 0x3f) as usize
     }
 }

src/instructions.rs

@@ -16,6 +16,12 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Option<Instr
         0b00100 => match instr.funct3() {
             // OP_IMM
             0b000 => Some(rvi::addi(core, instr)),
+            0b001 => match instr.funct6() {
+                // left-shift immediate
+                0b000000 => Some(rvi::slli(core, instr)),
+                _ => None,
+            },
+            0b111 => Some(rvi::andi(core, instr)),
             _ => None,
         },
         0b00110 => match instr.funct3() {
@@ -25,9 +31,21 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Option<Instr
         },
         0b01000 => match instr.funct3() {
             // STORE
+            0b000 => Some(rvi::sb(core, instr)),
             0b011 => Some(rvi::sd(core, instr)),
             _ => None,
         },
+        0b00000 => match instr.funct3() {
+            // LOAD
+            0b000 => Some(rvi::lb(core, instr)),
+            0b100 => Some(rvi::lbu(core, instr)),
+            _ => None,
+        },
+        0b11000 => match instr.funct3() {
+            // BRANCH
+            0b000 => Some(rvi::beq(core, instr)),
+            _ => None,
+        },
         0b01101 => Some(rvi::lui(core, instr)),
         0b11011 => Some(rvi::jal(core, instr)),
         _ => None,

src/instructions/rvi.rs

@@ -17,7 +17,7 @@ pub fn addi(core: &mut Core, instr: Instruction) -> InstructionResult {
         core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()),
     );
 
-    core.pc = core.pc.wrapping_add(4);
+    core.advance_pc();
 
     InstructionResult::Normal
 }
@@ -27,7 +27,15 @@ pub fn addiw(core: &mut Core, instr: Instruction) -> InstructionResult {
 
     core.reg_write(instr.rd(), res as i64 as u64);
 
-    core.pc = core.pc.wrapping_add(4);
+    core.advance_pc();
+
+    InstructionResult::Normal
+}
+
+pub fn andi(core: &mut Core, instr: Instruction) -> InstructionResult {
+    core.reg_write(instr.rd(), core.reg_read(instr.rs1()) & instr.imm_i());
+
+    core.advance_pc();
 
     InstructionResult::Normal
 }
@@ -41,12 +49,62 @@ pub fn sd(core: &mut Core, instr: Instruction) -> InstructionResult {
     }
 
     let page = (addr / 4096) as PageNum;
-    let offset = (addr & ((4096 / std::mem::size_of::<DWord>() as Addr) - 1)) as u16;
+    let offset = (addr / 8 & ((4096 / 8 as Addr) - 1)) as u16;
     let value = core.reg_read(instr.rs2());
 
     match core.mem.write_dword(page, offset, value) {
         Ok(_) => {
-            core.pc = core.pc.wrapping_add(4);
+            core.advance_pc();
+            InstructionResult::Normal
+        }
+        Err(_) => InstructionResult::Exception(()),
+    }
+}
+
+pub fn sb(core: &mut Core, instr: Instruction) -> InstructionResult {
+    let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
+
+    let page = (addr / 4096) as PageNum;
+    let offset = (addr & (4096 as Addr - 1)) as u16;
+    let value = core.reg_read(instr.rs2()) as u8;
+
+    match core.mem.write_byte(page, offset, value) {
+        Ok(_) => {
+            core.advance_pc();
+            InstructionResult::Normal
+        }
+        Err(_) => InstructionResult::Exception(()),
+    }
+}
+
+pub fn lb(core: &mut Core, instr: Instruction) -> InstructionResult {
+    let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
+
+    let page = (addr / 4096) as PageNum;
+    let offset = (addr & (4096 as Addr - 1)) as u16;
+
+    match core.mem.read_byte(page, offset) {
+        Ok(x) => {
+            let x = x as i8 as i64 as DWord;
+            core.reg_write(instr.rd(), x);
+            core.advance_pc();
+            InstructionResult::Normal
+        }
+        Err(_) => InstructionResult::Exception(()),
+    }
+}
+
+pub fn lbu(core: &mut Core, instr: Instruction) -> InstructionResult {
+    let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
+
+    let page = (addr / 4096) as PageNum;
+    let offset = (addr & (4096 as Addr - 1)) as u16;
+
+    match core.mem.read_byte(page, offset) {
+        Ok(x) => {
+            let x = x as DWord;
+            core.reg_write(instr.rd(), x);
+            core.advance_pc();
             InstructionResult::Normal
         }
         Err(_) => InstructionResult::Exception(()),
@@ -55,7 +113,7 @@ pub fn sd(core: &mut Core, instr: Instruction) -> InstructionResult {
 
 pub fn lui(core: &mut Core, instr: Instruction) -> InstructionResult {
     core.reg_write(instr.rd(), instr.imm_u());
-    core.pc = core.pc.wrapping_add(4);
+    core.advance_pc();
     InstructionResult::Normal
 }
 
@@ -64,3 +122,21 @@ pub fn jal(core: &mut Core, instr: Instruction) -> InstructionResult {
     core.pc = core.pc.wrapping_add(instr.imm_j());
     InstructionResult::Normal
 }
+
+pub fn beq(core: &mut Core, instr: Instruction) -> InstructionResult {
+    if core.reg_read(instr.rs1()) == core.reg_read(instr.rs2()) {
+        core.pc = core.pc.wrapping_add(instr.imm_b());
+    } else {
+        core.advance_pc();
+    }
+
+    InstructionResult::Normal
+}
+
+pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
+    core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());
+
+    core.advance_pc();
+
+    InstructionResult::Normal
+}

src/main.rs

@@ -9,6 +9,7 @@ use std::{
     fs::File,
     io::{self, Read},
     sync::Arc,
+    time::Duration,
 };
 
 use trve::{
@@ -17,6 +18,8 @@ use trve::{
     mem::{DeviceEntry, MemAccessFault, MemConfig, MemDeviceInterface, PageNum, Ram},
 };
 
+use crate::basic_uart::BasicUart;
+
 fn read_file_to_buffer(path: &str, buffer: &mut [u8]) -> io::Result<usize> {
     let mut file = File::open(path)?;
     let mut total_read = 0;
@@ -42,14 +45,24 @@ fn main() -> Result<(), Box<dyn Error>> {
     let buf = ram.buf_mut();
     read_file_to_buffer("./img", buf)?;
 
+    let uart = BasicUart::new();
+    let uart = uart.spawn_poller(Duration::from_millis(10));
+
     let mem_cfg = MemConfig {
         ram: Arc::new(ram),
         ram_start: 0x8000_0000 / 4096,
-        devices: Box::new([DeviceEntry {
-            base: 0,
-            size: 1,
-            interface: Arc::new(DbgOut),
-        }]),
+        devices: Box::new([
+            DeviceEntry {
+                base: 0,
+                size: 1,
+                interface: Arc::new(DbgOut),
+            },
+            DeviceEntry {
+                base: 1,
+                size: 1,
+                interface: uart,
+            },
+        ]),
     };
 
     let mut core = Core::new(mem_cfg);
@@ -59,6 +72,8 @@ fn main() -> Result<(), Box<dyn Error>> {
     Ok(())
 }
 
+mod basic_uart;
+
 struct DbgOut;
 
 impl MemDeviceInterface for DbgOut {