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Implement BLT

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taitep
2025-12-23 09:51:53 +01:00
parent 643a39c24a
commit c6da147d50
2 changed files with 18 additions and 0 deletions
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1
src/instructions.rs
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@@ -53,6 +53,7 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Option<Instr
// BRANCH // BRANCH
0b000 => Some(rvi::beq(core, instr)), 0b000 => Some(rvi::beq(core, instr)),
0b001 => Some(rvi::bne(core, instr)), 0b001 => Some(rvi::bne(core, instr)),
0b100 => Some(rvi::blt(core, instr)),
0b110 => Some(rvi::bltu(core, instr)), 0b110 => Some(rvi::bltu(core, instr)),
0b111 => Some(rvi::bgeu(core, instr)), 0b111 => Some(rvi::bgeu(core, instr)),
_ => None, _ => None,

17
src/instructions/rvi.rs
View File

@@ -93,12 +93,19 @@ pub fn auipc(core: &mut Core, instr: Instruction) -> InstructionResult {
pub fn jal(core: &mut Core, instr: Instruction) -> InstructionResult { pub fn jal(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(instr.rd(), core.pc.wrapping_add(4)); core.reg_write(instr.rd(), core.pc.wrapping_add(4));
eprintln!("set x{} to {:x}", instr.rd(), core.pc.wrapping_add(4));
core.pc = core.pc.wrapping_add(instr.imm_j()); core.pc = core.pc.wrapping_add(instr.imm_j());
InstructionResult::Normal InstructionResult::Normal
} }
pub fn jalr(core: &mut Core, instr: Instruction) -> InstructionResult { pub fn jalr(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(instr.rd(), core.pc.wrapping_add(4)); core.reg_write(instr.rd(), core.pc.wrapping_add(4));
eprintln!(
"origin: {:x}, reg: x{}={:x}",
core.pc,
instr.rs1(),
core.reg_read(instr.rs1())
);
core.pc = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()); core.pc = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
InstructionResult::Normal InstructionResult::Normal
} }
@@ -123,6 +130,16 @@ pub fn bne(core: &mut Core, instr: Instruction) -> InstructionResult {
InstructionResult::Normal InstructionResult::Normal
} }
pub fn blt(core: &mut Core, instr: Instruction) -> InstructionResult {
if (core.reg_read(instr.rs1()) as i64) < (core.reg_read(instr.rs2()) as i64) {
core.pc = core.pc.wrapping_add(instr.imm_b());
} else {
core.advance_pc();
}
InstructionResult::Normal
}
pub fn bgeu(core: &mut Core, instr: Instruction) -> InstructionResult { pub fn bgeu(core: &mut Core, instr: Instruction) -> InstructionResult {
if core.reg_read(instr.rs1()) >= core.reg_read(instr.rs2()) { if core.reg_read(instr.rs1()) >= core.reg_read(instr.rs2()) {
core.pc = core.pc.wrapping_add(instr.imm_b()); core.pc = core.pc.wrapping_add(instr.imm_b());