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Implement ANDI and BEQ

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taitep
2025-12-21 16:29:28 +01:00
parent acc267a460
commit c05ba60c3c
2 changed files with 24 additions and 0 deletions
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18
src/instructions/rvi.rs
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@@ -32,6 +32,14 @@ pub fn addiw(core: &mut Core, instr: Instruction) -> InstructionResult {
InstructionResult::Normal
}
pub fn andi(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(instr.rd(), core.reg_read(instr.rs1()) & instr.imm_i());
core.advance_pc();
InstructionResult::Normal
}
// TODO: Support misaligned memory access
pub fn sd(core: &mut Core, instr: Instruction) -> InstructionResult {
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
@@ -115,6 +123,16 @@ pub fn jal(core: &mut Core, instr: Instruction) -> InstructionResult {
InstructionResult::Normal
}
pub fn beq(core: &mut Core, instr: Instruction) -> InstructionResult {
if core.reg_read(instr.rs1()) == core.reg_read(instr.rs2()) {
core.pc = core.pc.wrapping_add(instr.imm_b());
} else {
core.advance_pc();
}
InstructionResult::Normal
}
pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());