From 9c4e2d17a2fda196cb5e936ae0693cdc1ee0b2f1 Mon Sep 17 00:00:00 2001
From: taitep <taitep@taitep.se>
Date: Tue, 21 Oct 2025 14:46:02 +0200
Subject: [PATCH] Add support for addiw and lui

---
 src/instructions/opcodes.rs |  1 +
 src/instructions/rvi.rs     | 31 ++++++++++++++++++++++++++-----
 2 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/src/instructions/opcodes.rs b/src/instructions/opcodes.rs
index 7115820..b5613f9 100644
--- a/src/instructions/opcodes.rs
+++ b/src/instructions/opcodes.rs
@@ -1,5 +1,6 @@
 //! Opcodes (unless compressed) have the last 2 bits stripped off as they are always 1s for non-compressed instructions.
 
 pub(super) const OP_IMM: u8 = 0b00100;
+pub(super) const OP_IMM_32: u8 = 0b00110;
 
 pub(super) const STORE: u8 = 0b01000;
diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs
index f82f1b3..365b133 100644
--- a/src/instructions/rvi.rs
+++ b/src/instructions/rvi.rs
@@ -5,17 +5,22 @@ use crate::{
     instructions::{
         OpcodeHandler,
         gen_tools::insert_funct3_splitter,
-        opcodes::{OP_IMM, STORE},
+        opcodes::{OP_IMM, OP_IMM_32, STORE},
     },
     mem::PageNum,
 };
 
 pub(super) fn add_instrs(list: &mut [OpcodeHandler; 32]) {
-    let funct3_split_op_imm = insert_funct3_splitter(&mut list[OP_IMM as usize].splitter);
-    funct3_split_op_imm[0b000].handler = Some(super::InstructionHandler { runner: addi }); // ADDI
+    let funct3_splitter = insert_funct3_splitter(&mut list[OP_IMM as usize].splitter); // OP-IMM
+    funct3_splitter[0b000].handler = Some(super::InstructionHandler { runner: addi }); // ADDI
 
-    let funct3_split_store = insert_funct3_splitter(&mut list[STORE as usize].splitter);
-    funct3_split_store[0b011].handler = Some(super::InstructionHandler { runner: sd }) // SD
+    let funct3_splitter = insert_funct3_splitter(&mut list[OP_IMM_32 as usize].splitter); // OP-IMM-32
+    funct3_splitter[0b000].handler = Some(super::InstructionHandler { runner: addiw }); //ADDIW
+
+    let funct3_splitter = insert_funct3_splitter(&mut list[STORE as usize].splitter); // STORE
+    funct3_splitter[0b011].handler = Some(super::InstructionHandler { runner: sd }); // SD
+
+    list[0b01101].handler = Some(super::InstructionHandler { runner: lui }); //LUI
 }
 
 fn addi(core: &mut Core, instr: Instruction) -> InstructionResult {
@@ -29,6 +34,16 @@ fn addi(core: &mut Core, instr: Instruction) -> InstructionResult {
     InstructionResult::Normal
 }
 
+fn addiw(core: &mut Core, instr: Instruction) -> InstructionResult {
+    let res = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()) as i32;
+
+    core.reg_write(instr.rd(), res as i64 as u64);
+
+    core.pc = core.pc.wrapping_add(4);
+
+    InstructionResult::Normal
+}
+
 // TODO: Support misaligned memory access
 fn sd(core: &mut Core, instr: Instruction) -> InstructionResult {
     let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
@@ -49,3 +64,9 @@ fn sd(core: &mut Core, instr: Instruction) -> InstructionResult {
         Err(_) => InstructionResult::Exception(()),
     }
 }
+
+fn lui(core: &mut Core, instr: Instruction) -> InstructionResult {
+    core.reg_write(instr.rd(), instr.imm_u());
+    core.pc = core.pc.wrapping_add(4);
+    InstructionResult::Normal
+}