Implement JALR, fix JAL, change how some stuff in instructions.rs is expressed
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@@ -16,11 +16,7 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Option<Instr
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0b00100 => match instr.funct3() {
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0b00100 => match instr.funct3() {
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// OP_IMM
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// OP_IMM
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0b000 => Some(rvi::addi(core, instr)),
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0b000 => Some(rvi::addi(core, instr)),
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0b001 => match instr.funct6() {
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0b001 => (instr.funct6() == 0).then(|| rvi::slli(core, instr)),
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// left-shift immediate
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0b000000 => Some(rvi::slli(core, instr)),
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_ => None,
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},
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0b111 => Some(rvi::andi(core, instr)),
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0b111 => Some(rvi::andi(core, instr)),
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_ => None,
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_ => None,
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},
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},
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@@ -47,8 +43,9 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Option<Instr
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_ => None,
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_ => None,
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},
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},
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0b01101 => Some(rvi::lui(core, instr)),
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0b01101 => Some(rvi::lui(core, instr)),
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0b11011 => Some(rvi::jal(core, instr)),
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0b00101 => Some(rvi::auipc(core, instr)),
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0b00101 => Some(rvi::auipc(core, instr)),
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0b11011 => Some(rvi::jal(core, instr)),
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0b11001 => (instr.funct3() == 0).then(|| rvi::jalr(core, instr)),
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_ => None,
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_ => None,
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}
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}
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}
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}
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@@ -117,15 +117,21 @@ pub fn lui(core: &mut Core, instr: Instruction) -> InstructionResult {
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InstructionResult::Normal
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InstructionResult::Normal
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}
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}
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pub fn auipc(core: &mut Core, instr: Instruction) -> InstructionResult {
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core.reg_write(instr.rd(), core.pc.wrapping_add(instr.imm_u()));
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core.advance_pc();
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InstructionResult::Normal
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}
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pub fn jal(core: &mut Core, instr: Instruction) -> InstructionResult {
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pub fn jal(core: &mut Core, instr: Instruction) -> InstructionResult {
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core.reg_write(instr.rd(), core.pc);
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core.reg_write(instr.rd(), core.pc.wrapping_add(4));
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core.pc = core.pc.wrapping_add(instr.imm_j());
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core.pc = core.pc.wrapping_add(instr.imm_j());
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InstructionResult::Normal
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InstructionResult::Normal
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}
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}
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pub fn auipc(core: &mut Core, instr: Instruction) -> InstructionResult {
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pub fn jalr(core: &mut Core, instr: Instruction) -> InstructionResult {
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core.reg_write(instr.rd(), core.pc.wrapping_add(instr.imm_u()));
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core.reg_write(instr.rd(), core.pc.wrapping_add(4));
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core.advance_pc();
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core.pc = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
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InstructionResult::Normal
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InstructionResult::Normal
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}
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}
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