(BIG CHANGE) memory handling has changed, MMIO is now a 2 level page table, misaligned access supported, addresses not internally split to page and offset immediately, all load/store instructions implemented. Might still have bugs
This commit is contained in:
83
src/main.rs
83
src/main.rs
@@ -7,10 +7,10 @@
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use std::{env, sync::Arc, time::Duration};
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use trve::{
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consts::{Byte, DWord, HWord, Word},
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consts::{Addr, Byte, DWord, HWord, Word},
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core::Core,
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exceptions::ExceptionType,
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mem::{DeviceEntry, MemConfig, MemDeviceInterface, PageNum, Ram},
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exceptions::MemoryExceptionType,
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mem::{MemConfig, MemDeviceInterface, MmioRoot, Ram},
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};
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use anyhow::{Result, bail};
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@@ -20,7 +20,7 @@ use crate::basic_uart::BasicUart;
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mod execload;
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fn main() -> Result<()> {
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let mut ram = Ram::try_new(16 * 1024 * 1024 / 4096)?;
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let mut ram = Ram::try_new(16 * 1024 * 1024)?;
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let buf = ram.buf_mut();
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let args: Vec<String> = env::args().collect();
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@@ -32,24 +32,16 @@ fn main() -> Result<()> {
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let entry_point = execload::load(&args[1], buf, 0x8000_0000)?;
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let mut mmio_root = MmioRoot::default();
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mmio_root.insert(0, Arc::new(DbgOut));
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let uart = BasicUart::new();
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let uart = uart.spawn_poller(Duration::from_millis(10));
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mmio_root.insert(0x10000, uart);
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let mem_cfg = MemConfig {
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ram: Arc::new(ram),
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ram_start: 0x8000_0000 / 4096,
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devices: Box::new([
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DeviceEntry {
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base: 0,
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size: 1,
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interface: Arc::new(DbgOut),
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},
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DeviceEntry {
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base: 1,
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size: 1,
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interface: uart,
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},
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]),
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mmio_root,
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};
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let mut core = Core::new(mem_cfg);
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@@ -64,64 +56,23 @@ mod basic_uart;
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struct DbgOut;
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impl MemDeviceInterface for DbgOut {
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fn write_dword(&self, page: PageNum, offset: u16, value: DWord) -> Result<(), ExceptionType> {
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eprintln!(
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"Wrote DWord {value:016x} to Debug-Out page {page}, offset {offset} (byte {})",
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offset * 8
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);
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fn write_dword(&self, addr: Addr, value: DWord) -> Result<(), MemoryExceptionType> {
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eprintln!("Wrote DWord {value:016x} to Debug-Out address {addr:x}");
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Ok(())
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}
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fn write_word(&self, page: PageNum, offset: u16, value: Word) -> Result<(), ExceptionType> {
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eprintln!(
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"Wrote Word {value:08x} to Debug-Out page {page}, offset {offset} (byte {})",
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offset * 4
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);
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fn write_word(&self, addr: Addr, value: Word) -> Result<(), MemoryExceptionType> {
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eprintln!("Wrote Word {value:08x} to Debug-Out address {addr:x}");
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Ok(())
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}
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fn write_hword(&self, page: PageNum, offset: u16, value: HWord) -> Result<(), ExceptionType> {
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eprintln!(
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"Wrote HWord {value:04x} to Debug-Out page {page}, offset {offset} (byte {})",
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offset * 2
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);
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fn write_hword(&self, addr: Addr, value: HWord) -> Result<(), MemoryExceptionType> {
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eprintln!("Wrote HWord {value:04x} to Debug-Out address {addr:x}");
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Ok(())
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}
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fn write_byte(&self, page: PageNum, offset: u16, value: Byte) -> Result<(), ExceptionType> {
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eprintln!("Wrote Byte {value:02x} to Debug-Out page {page}, offset {offset}");
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fn write_byte(&self, addr: Addr, value: Byte) -> Result<(), MemoryExceptionType> {
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eprintln!("Wrote Byte {value:02x} to Debug-Out address {addr:x}");
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Ok(())
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}
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fn read_dword(&self, _page: PageNum, _offset: u16) -> Result<DWord, ExceptionType> {
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Err(ExceptionType::LoadAccessFault)
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}
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fn read_word(&self, _page: PageNum, _offset: u16) -> Result<Word, ExceptionType> {
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Err(ExceptionType::LoadAccessFault)
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}
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fn read_hword(&self, _page: PageNum, _offset: u16) -> Result<HWord, ExceptionType> {
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Err(ExceptionType::LoadAccessFault)
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}
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fn read_byte(&self, _page: PageNum, _offset: u16) -> Result<Byte, ExceptionType> {
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Err(ExceptionType::LoadAccessFault)
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}
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fn get_atomic_word(
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&self,
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_page: PageNum,
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_offset: u16,
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) -> Result<&std::sync::atomic::AtomicU32, ExceptionType> {
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Err(ExceptionType::StoreAmoAccessFault)
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}
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fn get_atomic_dword(
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&self,
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_page: PageNum,
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_offset: u16,
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) -> Result<&std::sync::atomic::AtomicU64, ExceptionType> {
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Err(ExceptionType::StoreAmoAccessFault)
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}
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}
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