diff --git a/src/instructions.rs b/src/instructions.rs
index 5261dde..935a51f 100644
--- a/src/instructions.rs
+++ b/src/instructions.rs
@@ -34,6 +34,12 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Option<Instr
             0b011 => Some(rvi::sd(core, instr)),
             _ => None,
         },
+        0b00000 => match instr.funct3() {
+            // LOAD
+            0b000 => Some(rvi::lb(core, instr)),
+            0b100 => Some(rvi::lbu(core, instr)),
+            _ => None,
+        },
         0b01101 => Some(rvi::lui(core, instr)),
         0b11011 => Some(rvi::jal(core, instr)),
         _ => None,
diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs
index 89d142b..98fcb07 100644
--- a/src/instructions/rvi.rs
+++ b/src/instructions/rvi.rs
@@ -69,6 +69,40 @@ pub fn sb(core: &mut Core, instr: Instruction) -> InstructionResult {
     }
 }
 
+pub fn lb(core: &mut Core, instr: Instruction) -> InstructionResult {
+    let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
+
+    let page = (addr / 4096) as PageNum;
+    let offset = (addr & (4096 as Addr - 1)) as u16;
+
+    match core.mem.read_byte(page, offset) {
+        Ok(x) => {
+            let x = x as i8 as i64 as DWord;
+            core.reg_write(instr.rd(), x);
+            core.pc = core.pc.wrapping_add(4);
+            InstructionResult::Normal
+        }
+        Err(_) => InstructionResult::Exception(()),
+    }
+}
+
+pub fn lbu(core: &mut Core, instr: Instruction) -> InstructionResult {
+    let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
+
+    let page = (addr / 4096) as PageNum;
+    let offset = (addr & (4096 as Addr - 1)) as u16;
+
+    match core.mem.read_byte(page, offset) {
+        Ok(x) => {
+            let x = x as DWord;
+            core.reg_write(instr.rd(), x);
+            core.pc = core.pc.wrapping_add(4);
+            InstructionResult::Normal
+        }
+        Err(_) => InstructionResult::Exception(()),
+    }
+}
+
 pub fn lui(core: &mut Core, instr: Instruction) -> InstructionResult {
     core.reg_write(instr.rd(), instr.imm_u());
     core.pc = core.pc.wrapping_add(4);