base core state & instruction decoder

src/core.rs

@@ -0,0 +1,58 @@
+use crate::{
+    consts::{Addr, RegId, RegValue},
+    mem::MemConfig,
+};
+
+#[derive(PartialEq, Debug, Clone, Copy)]
+pub enum ExecutionStatus {
+    Running,
+    Paused,
+    Halted,
+}
+
+pub struct Core {
+    x_regs: [RegValue; 32],
+    pc: Addr,
+    mem: MemConfig,
+    exec_status: ExecutionStatus,
+}
+
+impl Core {
+    pub fn new(mem: MemConfig) -> Self {
+        Self {
+            x_regs: [0; 32],
+            pc: 0,
+            mem,
+            exec_status: ExecutionStatus::Halted,
+        }
+    }
+
+    pub fn reset(&mut self, pc: Addr) {
+        self.pc = pc;
+        self.exec_status = ExecutionStatus::Running;
+    }
+
+    pub fn resume(&mut self) -> ExecutionStatus {
+        if self.exec_status == ExecutionStatus::Halted {
+            ExecutionStatus::Halted
+        } else {
+            self.exec_status = ExecutionStatus::Running;
+            ExecutionStatus::Running
+        }
+    }
+
+    pub fn exec_status(&self) -> ExecutionStatus {
+        self.exec_status
+    }
+
+    fn reg_read(&self, id: RegId) -> RegValue {
+        self.x_regs[id as usize]
+    }
+
+    fn reg_write(&mut self, id: RegId, value: RegValue) {
+        if id == 0 {
+            return;
+        }
+        self.x_regs[id as usize] = value;
+    }
+}