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Make a dedicated function for advancing the PC by one instruction

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taitep
2025-12-21 16:00:54 +01:00
parent 390a2b3228
commit 25c3b9f5e2
2 changed files with 12 additions and 8 deletions
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4
src/core.rs
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@@ -92,4 +92,8 @@ impl Core {
} }
self.x_regs[id as usize] = value; self.x_regs[id as usize] = value;
} }
pub(crate) fn advance_pc(&mut self) {
self.pc = self.pc.wrapping_add(4);
}
} }

16
src/instructions/rvi.rs
View File

@@ -17,7 +17,7 @@ pub fn addi(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()), core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()),
); );
core.pc = core.pc.wrapping_add(4); core.advance_pc();
InstructionResult::Normal InstructionResult::Normal
} }
@@ -27,7 +27,7 @@ pub fn addiw(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(instr.rd(), res as i64 as u64); core.reg_write(instr.rd(), res as i64 as u64);
core.pc = core.pc.wrapping_add(4); core.advance_pc();
InstructionResult::Normal InstructionResult::Normal
} }
@@ -46,7 +46,7 @@ pub fn sd(core: &mut Core, instr: Instruction) -> InstructionResult {
match core.mem.write_dword(page, offset, value) { match core.mem.write_dword(page, offset, value) {
Ok(_) => { Ok(_) => {
core.pc = core.pc.wrapping_add(4); core.advance_pc();
InstructionResult::Normal InstructionResult::Normal
} }
Err(_) => InstructionResult::Exception(()), Err(_) => InstructionResult::Exception(()),
@@ -62,7 +62,7 @@ pub fn sb(core: &mut Core, instr: Instruction) -> InstructionResult {
match core.mem.write_byte(page, offset, value) { match core.mem.write_byte(page, offset, value) {
Ok(_) => { Ok(_) => {
core.pc = core.pc.wrapping_add(4); core.advance_pc();
InstructionResult::Normal InstructionResult::Normal
} }
Err(_) => InstructionResult::Exception(()), Err(_) => InstructionResult::Exception(()),
@@ -79,7 +79,7 @@ pub fn lb(core: &mut Core, instr: Instruction) -> InstructionResult {
Ok(x) => { Ok(x) => {
let x = x as i8 as i64 as DWord; let x = x as i8 as i64 as DWord;
core.reg_write(instr.rd(), x); core.reg_write(instr.rd(), x);
core.pc = core.pc.wrapping_add(4); core.advance_pc();
InstructionResult::Normal InstructionResult::Normal
} }
Err(_) => InstructionResult::Exception(()), Err(_) => InstructionResult::Exception(()),
@@ -96,7 +96,7 @@ pub fn lbu(core: &mut Core, instr: Instruction) -> InstructionResult {
Ok(x) => { Ok(x) => {
let x = x as DWord; let x = x as DWord;
core.reg_write(instr.rd(), x); core.reg_write(instr.rd(), x);
core.pc = core.pc.wrapping_add(4); core.advance_pc();
InstructionResult::Normal InstructionResult::Normal
} }
Err(_) => InstructionResult::Exception(()), Err(_) => InstructionResult::Exception(()),
@@ -105,7 +105,7 @@ pub fn lbu(core: &mut Core, instr: Instruction) -> InstructionResult {
pub fn lui(core: &mut Core, instr: Instruction) -> InstructionResult { pub fn lui(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(instr.rd(), instr.imm_u()); core.reg_write(instr.rd(), instr.imm_u());
core.pc = core.pc.wrapping_add(4); core.advance_pc();
InstructionResult::Normal InstructionResult::Normal
} }
@@ -118,7 +118,7 @@ pub fn jal(core: &mut Core, instr: Instruction) -> InstructionResult {
pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult { pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt()); core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());
core.pc = core.pc.wrapping_add(4); core.advance_pc();
InstructionResult::Normal InstructionResult::Normal
} }