Implement SRLI
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@@ -79,6 +79,12 @@ pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
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InstructionResult::Normal
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}
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pub fn srli(core: &mut Core, instr: Instruction) -> InstructionResult {
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core.reg_write(instr.rd(), core.reg_read(instr.rs1()) >> instr.imm_shamt());
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core.advance_pc();
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InstructionResult::Normal
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}
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pub fn lui(core: &mut Core, instr: Instruction) -> InstructionResult {
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core.reg_write(instr.rd(), instr.imm_u());
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core.advance_pc();
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