taitep/trve
1
1
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

EXCEPTION SYSTEM (initial version - may change later)

Browse Source
This commit is contained in:
taitep
2025-12-24 13:56:41 +01:00
parent 3f789442c0
commit 09d9064372
11 changed files with 338 additions and 332 deletions
Download Patch File Download Diff File Expand all files Collapse all files

88
src/instructions.rs
View File

@@ -7,67 +7,81 @@
mod rvi;
use crate::{
core::{Core, InstructionResult},
core::Core,
decode::Instruction,
exceptions::ExceptionType::{self, IllegalInstruction},
};
pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Option<InstructionResult> {
pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Result<(), ExceptionType> {
match instr.opcode_noncompressed() {
0b01100 => match (instr.funct7(), instr.funct3()) {
// OP
(0b0000000, 0b000) => Some(rvi::add(core, instr)),
(0b0100000, 0b000) => Some(rvi::sub(core, instr)),
(0b0000000, 0b111) => Some(rvi::and(core, instr)),
(0b0000000, 0b110) => Some(rvi::or(core, instr)),
_ => None,
(0b0000000, 0b000) => rvi::add(core, instr),
(0b0100000, 0b000) => rvi::sub(core, instr),
(0b0000000, 0b111) => rvi::and(core, instr),
(0b0000000, 0b110) => rvi::or(core, instr),
_ => Err(IllegalInstruction),
},
0b00100 => match instr.funct3() {
// OP_IMM
0b000 => Some(rvi::addi(core, instr)),
0b001 => (instr.funct6() == 0).then(|| rvi::slli(core, instr)),
0b000 => rvi::addi(core, instr),
0b001 => {
if instr.funct6() == 0 {
rvi::slli(core, instr)
} else {
Err(IllegalInstruction)
}
}
0b101 => match instr.funct6() {
// immediate right-shift
0b000000 => Some(rvi::srli(core, instr)),
_ => None,
0b000000 => rvi::srli(core, instr),
_ => Err(IllegalInstruction),
},
0b111 => Some(rvi::andi(core, instr)),
_ => None,
0b111 => rvi::andi(core, instr),
_ => Err(IllegalInstruction),
},
0b00110 => match instr.funct3() {
// OP_IMM_32
0b000 => Some(rvi::addiw(core, instr)),
_ => None,
0b000 => rvi::addiw(core, instr),
_ => Err(IllegalInstruction),
},
0b01000 => match instr.funct3() {
// STORE
0b000 => Some(rvi::sb(core, instr)),
0b001 => Some(rvi::sh(core, instr)),
0b010 => Some(rvi::sw(core, instr)),
0b011 => Some(rvi::sd(core, instr)),
_ => None,
0b000 => rvi::sb(core, instr),
0b001 => rvi::sh(core, instr),
0b010 => rvi::sw(core, instr),
0b011 => rvi::sd(core, instr),
_ => Err(IllegalInstruction),
},
0b00000 => match instr.funct3() {
// LOAD
0b000 => Some(rvi::lb(core, instr)),
0b100 => Some(rvi::lbu(core, instr)),
0b001 => Some(rvi::lh(core, instr)),
0b010 => Some(rvi::lw(core, instr)),
0b011 => Some(rvi::ld(core, instr)),
_ => None,
0b000 => rvi::lb(core, instr),
0b100 => rvi::lbu(core, instr),
0b001 => rvi::lh(core, instr),
0b010 => rvi::lw(core, instr),
0b011 => rvi::ld(core, instr),
_ => Err(IllegalInstruction),
},
0b11000 => match instr.funct3() {
// BRANCH
0b000 => Some(rvi::beq(core, instr)),
0b001 => Some(rvi::bne(core, instr)),
0b100 => Some(rvi::blt(core, instr)),
0b110 => Some(rvi::bltu(core, instr)),
0b111 => Some(rvi::bgeu(core, instr)),
_ => None,
0b000 => rvi::beq(core, instr),
0b001 => rvi::bne(core, instr),
0b100 => rvi::blt(core, instr),
0b110 => rvi::bltu(core, instr),
0b111 => rvi::bgeu(core, instr),
_ => Err(IllegalInstruction),
},
0b01101 => Some(rvi::lui(core, instr)),
0b00101 => Some(rvi::auipc(core, instr)),
0b11011 => Some(rvi::jal(core, instr)),
0b11001 => (instr.funct3() == 0).then(|| rvi::jalr(core, instr)),
_ => None,
0b01101 => rvi::lui(core, instr),
0b00101 => rvi::auipc(core, instr),
0b11011 => rvi::jal(core, instr),
// 0b11001 => (instr.funct3() == 0).then(|| rvi::jalr(core, instr)),
0b11001 => {
if instr.funct3() == 0 {
rvi::jalr(core, instr)
} else {
Err(IllegalInstruction)
}
}
_ => Err(IllegalInstruction),
}
}