EXCEPTION SYSTEM (initial version - may change later)
This commit is contained in:
@@ -7,177 +7,145 @@
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use crate::{
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consts::{Addr, Byte, DWord, HWord, Word},
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core::Core,
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instructions::{Instruction, InstructionResult},
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exceptions::ExceptionType,
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instructions::Instruction,
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mem::PageNum,
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};
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// TODO: Support misaligned memory access
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pub fn sd(core: &mut Core, instr: Instruction) -> InstructionResult {
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pub fn sd(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
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let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
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if !addr.is_multiple_of(std::mem::size_of::<DWord>() as Addr) {
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return InstructionResult::Exception(());
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return Err(ExceptionType::StoreAmoAddressMisaligned);
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}
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let page = (addr / 4096) as PageNum;
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let offset = (addr / 8 & ((4096 / 8 as Addr) - 1)) as u16;
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let value = core.reg_read(instr.rs2());
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match core.mem.write_dword(page, offset, value) {
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Ok(_) => {
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core.advance_pc();
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InstructionResult::Normal
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}
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Err(_) => InstructionResult::Exception(()),
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}
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core.mem.write_dword(page, offset, value)?;
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core.advance_pc();
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Ok(())
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}
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pub fn ld(core: &mut Core, instr: Instruction) -> InstructionResult {
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pub fn ld(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
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let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
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if !addr.is_multiple_of(std::mem::size_of::<DWord>() as Addr) {
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return InstructionResult::Exception(());
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return Err(ExceptionType::LoadAddressMisaligned);
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}
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let page = (addr / 4096) as PageNum;
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let offset = (addr / 8 & ((4096 / 8 as Addr) - 1)) as u16;
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match core.mem.read_dword(page, offset) {
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Ok(x) => {
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core.reg_write(instr.rd(), x);
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core.advance_pc();
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InstructionResult::Normal
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}
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Err(_) => InstructionResult::Exception(()),
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}
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core.reg_write(instr.rd(), core.mem.read_dword(page, offset)?);
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core.advance_pc();
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Ok(())
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}
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pub fn sw(core: &mut Core, instr: Instruction) -> InstructionResult {
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pub fn sw(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
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let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
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if !addr.is_multiple_of(std::mem::size_of::<Word>() as Addr) {
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return InstructionResult::Exception(());
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return Err(ExceptionType::StoreAmoAddressMisaligned);
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}
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let page = (addr / 4096) as PageNum;
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let offset = (addr / 4 & ((4096 / 4 as Addr) - 1)) as u16;
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let value = core.reg_read(instr.rs2()) as Word;
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match core.mem.write_word(page, offset, value) {
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Ok(_) => {
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core.advance_pc();
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InstructionResult::Normal
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}
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Err(_) => InstructionResult::Exception(()),
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}
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core.mem.write_word(page, offset, value)?;
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core.advance_pc();
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Ok(())
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}
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pub fn lw(core: &mut Core, instr: Instruction) -> InstructionResult {
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pub fn lw(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
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let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
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if !addr.is_multiple_of(std::mem::size_of::<Word>() as Addr) {
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return InstructionResult::Exception(());
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return Err(ExceptionType::LoadAddressMisaligned);
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}
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let page = (addr / 4096) as PageNum;
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let offset = (addr / 4 & ((4096 / 4 as Addr) - 1)) as u16;
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match core.mem.read_word(page, offset) {
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Ok(x) => {
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core.reg_write(instr.rd(), x as i32 as i64 as DWord);
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core.advance_pc();
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InstructionResult::Normal
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}
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Err(_) => InstructionResult::Exception(()),
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}
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core.reg_write(
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instr.rd(),
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core.mem.read_word(page, offset)? as i32 as i64 as DWord,
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);
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core.advance_pc();
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Ok(())
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}
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pub fn sh(core: &mut Core, instr: Instruction) -> InstructionResult {
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pub fn sh(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
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let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
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if !addr.is_multiple_of(std::mem::size_of::<HWord>() as Addr) {
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return InstructionResult::Exception(());
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return Err(ExceptionType::StoreAmoAddressMisaligned);
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}
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let page = (addr / 4096) as PageNum;
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let offset = (addr / 2 & ((4096 / 2 as Addr) - 1)) as u16;
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let value = core.reg_read(instr.rs2()) as HWord;
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match core.mem.write_hword(page, offset, value) {
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Ok(_) => {
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core.advance_pc();
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InstructionResult::Normal
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}
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Err(_) => InstructionResult::Exception(()),
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}
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core.mem.write_hword(page, offset, value)?;
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core.advance_pc();
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Ok(())
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}
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pub fn lh(core: &mut Core, instr: Instruction) -> InstructionResult {
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pub fn lh(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
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let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
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if !addr.is_multiple_of(std::mem::size_of::<HWord>() as Addr) {
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return InstructionResult::Exception(());
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return Err(ExceptionType::LoadAddressMisaligned);
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}
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let page = (addr / 4096) as PageNum;
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let offset = (addr / 2 & ((4096 / 2 as Addr) - 1)) as u16;
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match core.mem.read_hword(page, offset) {
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Ok(x) => {
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core.reg_write(instr.rd(), x as i16 as i64 as DWord);
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core.advance_pc();
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InstructionResult::Normal
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}
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Err(_) => InstructionResult::Exception(()),
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}
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core.reg_write(
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instr.rd(),
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core.mem.read_hword(page, offset)? as i16 as i64 as DWord,
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);
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core.advance_pc();
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Ok(())
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}
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pub fn sb(core: &mut Core, instr: Instruction) -> InstructionResult {
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pub fn sb(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
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let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
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let page = (addr / 4096) as PageNum;
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let offset = (addr & (4096 as Addr - 1)) as u16;
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let value = core.reg_read(instr.rs2()) as Byte;
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match core.mem.write_byte(page, offset, value) {
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Ok(_) => {
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core.advance_pc();
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InstructionResult::Normal
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}
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Err(_) => InstructionResult::Exception(()),
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}
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core.mem.write_byte(page, offset, value)?;
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core.advance_pc();
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Ok(())
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}
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pub fn lb(core: &mut Core, instr: Instruction) -> InstructionResult {
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pub fn lb(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
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let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
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let page = (addr / 4096) as PageNum;
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let offset = (addr & (4096 as Addr - 1)) as u16;
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match core.mem.read_byte(page, offset) {
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Ok(x) => {
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let x = x as i8 as i64 as DWord;
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core.reg_write(instr.rd(), x);
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core.advance_pc();
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InstructionResult::Normal
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}
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Err(_) => InstructionResult::Exception(()),
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}
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core.reg_write(
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instr.rd(),
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core.mem.read_byte(page, offset)? as i8 as i64 as DWord,
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);
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core.advance_pc();
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Ok(())
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}
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pub fn lbu(core: &mut Core, instr: Instruction) -> InstructionResult {
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pub fn lbu(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
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let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
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let page = (addr / 4096) as PageNum;
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let offset = (addr & (4096 as Addr - 1)) as u16;
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match core.mem.read_byte(page, offset) {
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Ok(x) => {
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let x = x as DWord;
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core.reg_write(instr.rd(), x);
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core.advance_pc();
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InstructionResult::Normal
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}
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Err(_) => InstructionResult::Exception(()),
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}
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core.reg_write(instr.rd(), core.mem.read_byte(page, offset)? as DWord);
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core.advance_pc();
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Ok(())
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}
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