taitep/trve
1
1
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Add some stuff to the readme

Browse Source
This commit is contained in:
taitep
2025-12-21 13:03:18 +01:00
parent e8da0fc396
commit 00976cb7cd
1 changed files with 17 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
README.md
View File

@@ -1,3 +1,19 @@
# trve
RISC-V Emulator. The goal is to support at least RV64GC and be able to run Linux, potentially more. No plans for RV32I or RV32/64E.
taitep's RISC-V Emulator.
The goal is to support at least RV64GC and be able to run Linux,
potentially more. No plans for RV32I or RV32/64E.
## Current Use
Currently, the emulator is nowhere near complete,
its not even at rv64i, but it does work for a subset of it.
The emulator will load a raw binary image from the file `./img` into RAM,
which starts at 0x80000000 and is currently 1MiB,
and start execution at the start of the image/ram.
There is also a debug out page starting at `0x00000000`-`0x00001000`.
Anything written to it will be logged out in hex.
Currently there is no input, altho i might get around to making
an early UART kinda soon.